A three-dimensional integrated circuit (3D IC) is a
MOS
MOS or Mos may refer to:
Technology
* MOSFET (metal–oxide–semiconductor field-effect transistor), also known as the MOS transistor
* Mathematical Optimization Society
* Model output statistics, a weather-forecasting technique
* MOS (filmm ...
(metal-oxide semiconductor)
integrated circuit (IC) manufactured by stacking as many as 16 or more ICs and interconnecting them vertically using, for instance,
through-silicon via
In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high-performance interconnect techniques used as an alternative ...
s (TSVs) or Cu-Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. The 3D IC is one of several 3D integration schemes that exploit the z-direction to achieve electrical performance benefits in
microelectronics
Microelectronics is a subfield of electronics. As the name suggests, microelectronics relates to the study and manufacture (or microfabrication) of very small electronic designs and components. Usually, but not always, this means micrometre-s ...
and
nanoelectronics
Nanoelectronics refers to the use of nanotechnology in electronic components. The term covers a diverse set of devices and materials, with the common characteristic that they are so small that inter-atomic interactions and quantum mechanical p ...
.
3D integrated circuits can be classified by their level of interconnect hierarchy at the global (
package), intermediate (bond pad) and local (
transistor
upright=1.4, gate (G), body (B), source (S) and drain (D) terminals. The gate is separated from the body by an insulating layer (pink).
A transistor is a semiconductor device used to Electronic amplifier, amplify or electronic switch, switch ...
) level. In general, 3D integration is a broad term that includes such technologies as 3D wafer-level packaging (3DWLP); 2.5D and 3D interposer-based integration; 3D stacked ICs (3D-SICs); monolithic 3D ICs; 3D heterogeneous integration; and 3D systems integration.
International organizations such as the Jisso Technology Roadmap Committee (JIC) and the
International Technology Roadmap for Semiconductors
The International Technology Roadmap for Semiconductors (ITRS) is a set of documents produced by a group of semiconductor industry experts. These experts are representative of the sponsoring organisations which include the Semiconductor Industry A ...
(ITRS) have worked to classify the various 3D integration technologies to further the establishment of standards and roadmaps of 3D integration. As of the 2010s, 3D ICs are widely used for
NAND flash memory and in
mobile device
A mobile device (or handheld computer) is a computer small enough to hold and operate in the hand. Mobile devices typically have a flat LCD or OLED screen, a touchscreen interface, and digital or physical buttons. They may also have a physica ...
s.
Types
3D ICs vs. 3D packaging
3D packaging refers to 3D integration schemes that rely on traditional interconnection methods such as
wire bonding
Wire bonding is the method of making interconnections between an integrated circuit (IC) or other semiconductor device and its packaging during semiconductor device fabrication. Although less common, wire bonding can be used to connect an IC ...
and
flip chip
Flip chip, also known as controlled collapse chip connection or its abbreviation, C4, is a method for interconnecting dies such as semiconductor devices, IC chips, integrated passive devices and microelectromechanical systems (MEMS), to exter ...
to achieve vertical stacking. 3D packaging can be divided into 3D
system in package (3D SiP) and 3D
wafer level package (3D WLP). 3D SiPs that have been in mainstream manufacturing for some time and have a well-established infrastructure include stacked memory dies interconnected with wire bonds and
package on package
Package on a package (PoP) is an integrated circuit packaging method to vertically combine discrete logic and memory ball grid array (BGA) packages. Two or more packages are installed atop each other, i.e. stacked, with a standard interface to rout ...
(PoP) configurations interconnected with wire bonds or flip chip technology. PoP is used for vertically integrating disparate technologies. 3D WLP uses wafer level processes such as
redistribution layer
A redistribution layer (RDL) is an extra metal layer on an integrated circuit that makes its IO pads available in other locations of the chip, for better access to the pads where necessary.
When an integrated circuit is manufactured, it usually h ...
s (RDLs) and wafer bumping processes to form interconnects.
2.5D
interposer is a 3D WLP that interconnects dies side-by-side on a silicon, glass, or organic interposer using through silicon vias (TSVs) and an RDL. In all types of 3D packaging, chips in the package communicate using off-chip signaling, much as if they were mounted in separate packages on a normal circuit board.
3D ICs can be divided into 3D Stacked ICs (3D SIC), which refers to stacking IC chips using TSV interconnects, and monolithic 3D ICs, which use fab processes to realize 3D interconnects at the local levels of the on-chip wiring hierarchy as set forth by the ITRS, this results in direct vertical interconnects between device layers. The first examples of a monolithic approach are seen in
Samsung
The Samsung Group (or simply Samsung) ( ko, 삼성 ) is a South Korean multinational manufacturing conglomerate headquartered in Samsung Town, Seoul, South Korea. It comprises numerous affiliated businesses, most of them united under the ...
's 3D
V-NAND
Flash memory is an electronic non-volatile computer memory storage medium that can be electrically erased and reprogrammed. The two main types of flash memory, NOR flash and NAND flash, are named for the NOR and NAND logic gates. Both us ...
devices.
As of the 2010s, 3D IC packages are widely used for
NAND flash
Flash memory is an electronic non-volatile computer memory storage medium that can be electrically erased and reprogrammed. The two main types of flash memory, NOR flash and NAND flash, are named for the NOR and NAND logic gates. Both use ...
memory in
mobile devices
A mobile device (or handheld computer) is a computer small enough to hold and operate in the hand. Mobile devices typically have a flat LCD or OLED screen, a touchscreen interface, and digital or physical buttons. They may also have a physical ...
.
3D SiCs
The digital electronics market requires a higher density
semiconductor memory chip to cater to recently released
CPU components, and the multiple die stacking technique has been suggested as a solution to this problem.
JEDEC
The JEDEC Solid State Technology Association is an independent semiconductor engineering trade organization and standardization body headquartered in Arlington County, Virginia, United States.
JEDEC has over 300 members, including some of the w ...
disclosed the upcoming
DRAM technology includes the "3D SiC" die stacking plan at "Server Memory Forum", November 1–2, 2011, Santa Clara, CA. In August 2014,
Samsung Electronics
Samsung Electronics Co., Ltd. (, sometimes shortened to SEC and stylized as SΛMSUNG) is a South Korean multinational electronics corporation headquartered in Yeongtong-gu, Suwon, South Korea. It is the pinnacle of the Samsung chaebol, a ...
started producing 64GB
SDRAM modules for servers based on emerging
DDR4
Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) is a type of synchronous dynamic random-access memory with a high bandwidth (" double data rate") interface.
Released to the market in 2014, it is a variant of dynamic ra ...
(double-data rate 4) memory using 3D TSV package technology. Newer proposed standards for 3D stacked DRAM include Wide I/O, Wide I/O 2,
Hybrid Memory Cube,
High Bandwidth Memory
High Bandwidth Memory (HBM) is a high-speed computer memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM) initially from Samsung, AMD and SK Hynix. It is used in conjunction with high-performance graphics accelerator ...
.
Monolithic 3D ICs
Monolithic 3D ICs are built in layers on a single
semiconductor wafer
In electronics, a wafer (also called a slice or substrate) is a thin slice of semiconductor, such as a crystalline silicon (c-Si), used for the fabrication of integrated circuits and, in photovoltaics, to manufacture solar cells. The wafer serv ...
, which is then
diced
Dicing is a culinary knife cut in which the food item is cut into small blocks or dice. This may be done for aesthetic reasons or to create uniformly sized pieces to ensure even cooking. Dicing allows for distribution of flavour and texture ...
into 3D ICs. There is only one substrate, hence no need for aligning, thinning, bonding, or
through-silicon via
In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high-performance interconnect techniques used as an alternative ...
s. Process temperature limitations are addressed by partitioning the transistor fabrication into two phases. A high temperature phase which is done before layer transfer followed by a layer transfer usin
ion-cut also known as layer transfer, which has been used to produce
Silicon on Insulator (SOI) wafers for the past two decades. Multiple thin (10s–100s nanometer scale) layers of virtually defect-free Silicon can be created by utilizing low temperature (<400℃) bond and cleave techniques, and placed on top of active transistor circuitry. Follow by finalizing the transistors using etch and deposition processes. This monolithic 3D IC technology has been researched at
Stanford University under a
DARPA
The Defense Advanced Research Projects Agency (DARPA) is a research and development agency of the United States Department of Defense responsible for the development of emerging technologies for use by the military.
Originally known as the Ad ...
-sponsored grant.
CEA-Leti is also developing monolithic 3D IC approaches, called sequential 3D IC. In 2014, the French research institute introduced its CoolCube™, a low-temperature process flow that provides a true path to 3DVLSI. At Stanford University, researchers are designing monolithic 3D ICs using carbon nanotube (CNT) structures vs. silicon using a wafer-scale low temperature CNT transfer processes that can be done at 120℃.
In general, monolithic 3D ICs are still a developing technology and are considered by most to be several years away from production.
Manufacturing technologies for 3D SiCs
There are several methods for 3D IC design, including recrystallization and wafer bonding methods. There are two major types of wafer bonding, Cu-Cu connections (copper-to-copper connections between stacked ICs, used in TSVs)
and
through-silicon via
In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high-performance interconnect techniques used as an alternative ...
(TSV). As of 2014, a number of memory products such as
High Bandwidth Memory
High Bandwidth Memory (HBM) is a high-speed computer memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM) initially from Samsung, AMD and SK Hynix. It is used in conjunction with high-performance graphics accelerator ...
(HBM) and the
Hybrid Memory Cube have been launched that implement 3D IC stacking with TSVs. There are a number of key stacking approaches being implemented and explored. These include die-to-die, die-to-wafer, and wafer-to-wafer.
; Die-to-Die: Electronic components are built on multiple die, which are then aligned and bonded. Thinning and TSV creation may be done before or after bonding. One advantage of die-to-die is that each component die can be tested first, so that one bad die does not ruin an entire stack.
Moreover, each die in the 3D IC can be binned beforehand, so that they can be mixed and matched to optimize power consumption and performance (e.g. matching multiple dice from the low power process corner for a mobile application).
; Die-to-Wafer: Electronic components are built on two semiconductor wafers. One wafer is diced; the singulated
dice are aligned and bonded onto die sites of the second wafer. As in the wafer-on-wafer method, thinning and TSV creation are performed either before or after bonding. Additional die may be added to the stacks before dicing.
; Wafer-to-Wafer:
Electronic components are built on two or more
semiconductor wafers, which are then aligned, bonded, and
diced
Dicing is a culinary knife cut in which the food item is cut into small blocks or dice. This may be done for aesthetic reasons or to create uniformly sized pieces to ensure even cooking. Dicing allows for distribution of flavour and texture ...
into 3D ICs. Each wafer may be thinned before or after bonding. Vertical
connections are either built into the wafers before bonding or else created in the stack after bonding. These "
through-silicon via
In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high-performance interconnect techniques used as an alternative ...
s" (TSVs) pass through the silicon substrate(s) between active layers and/or between an active layer and an external bond pad. Wafer-to-wafer bonding can reduce yields, since if any 1 of ''N'' chips in a 3D IC are defective, the entire 3D IC will be defective. Moreover, the wafers must be the same size, but many exotic materials (e.g. III-Vs) are manufactured on much smaller wafers than
CMOS logic
Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss", ) is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFE ...
or
DRAM (typically 300 mm), complicating heterogeneous integration.
Benefits
While traditional
CMOS scaling processes improves signal propagation speed, scaling from current manufacturing and chip-design technologies is becoming more difficult and costly, in part because of power-density constraints, and in part because interconnects do not become faster while transistors do.
3D ICs address the scaling challenge by stacking 2D dies and connecting them in the 3rd dimension. This promises to speed up communication between layered chips, compared to planar layout.
3D ICs promise many significant benefits, including:
; Footprint: More functionality fits into a small space. This extends
Moore's law and enables a new generation of tiny but powerful devices.
; Cost: Partitioning a large chip into multiple smaller dies with 3D stacking can improve the yield and reduce the fabrication cost if individual dies are tested separately.
; Heterogeneous integration: Circuit layers can be built with different processes, or even on different types of wafers. This means that components can be optimized to a much greater degree than if they were built together on a single wafer. Moreover, components with incompatible manufacturing could be combined in a single 3D IC.
; Shorter interconnect: The average wire length is reduced. Common figures reported by researchers are on the order of 10–15%, but this reduction mostly applies to longer interconnect, which may affect circuit delay by a greater amount. Given that 3D wires have much higher capacitance than conventional in-die wires, circuit delay may or may not improve.
; Power: Keeping a signal on-chip can reduce its
power consumption
Electric energy consumption is the form of energy consumption that uses electrical energy. Electric energy consumption is the actual energy demand made on existing electricity supply for transportation, residential, industrial, commercial, and ot ...
by 10–100 times.
Shorter wires also reduce power consumption by producing less
parasitic capacitance.
Reducing the power budget leads to less heat generation, extended battery life, and lower cost of operation.
; Design: The vertical dimension adds a higher order of connectivity and offers new design possibilities.
; Circuit security: 3D integration can achieve
security through obscurity
Security through obscurity (or security by obscurity) is the reliance in security engineering on design or implementation secrecy as the main method of providing security to a system or component.
History
An early opponent of security through o ...
; the stacked structure complicates attempts to
reverse engineer
Reverse engineering (also known as backwards engineering or back engineering) is a process or method through which one attempts to understand through deductive reasoning how a previously made device, process, system, or piece of software accompli ...
the circuitry. Sensitive circuits may also be divided among the layers in such a way as to obscure the function of each layer.
Moreover, 3D integration allows to integrate dedicated,
system monitor
A system monitor is a hardware or software component used to monitor system resources and performance in a computer system.
Among the management issues regarding use of system monitoring tools are resource usage and privacy.
Overview
Software ...
-like features in separate layers.
The objective here is to implement some kind of hardware
firewall
Firewall may refer to:
* Firewall (computing), a technological barrier designed to prevent unauthorized or unwanted communications between computer networks or hosts
* Firewall (construction), a barrier inside a building, designed to limit the spr ...
for any commodity components/chips to be monitored at runtime, seeking to protect the whole
electronic system
Electronic may refer to:
*Electronics, the science of how to control electric energy in semiconductor
* ''Electronics'' (magazine), a defunct American trade journal
*Electronic storage, the storage of data using an electronic device
*Electronic co ...
against run-time attacks as well as malicious hardware modifications.
;
Bandwidth
Bandwidth commonly refers to:
* Bandwidth (signal processing) or ''analog bandwidth'', ''frequency bandwidth'', or ''radio bandwidth'', a measure of the width of a frequency range
* Bandwidth (computing), the rate of data transfer, bit rate or thr ...
: 3D integration allows large numbers of vertical vias between the layers. This allows construction of wide bandwidth
buses between functional blocks in different layers. A typical example would be a processor+memory 3D stack, with the cache memory stacked on top of the processor. This arrangement allows a bus much wider than the typical 128 or 256 bits between the cache and processor.
Wide buses in turn alleviate the
memory wall
Random-access memory (RAM; ) is a form of computer memory that can be read and changed in any order, typically used to store working data and machine code. A random-access memory device allows data items to be read or written in almost the ...
problem.
Challenges
Because this technology is new, it carries new challenges, including:
; Cost: While cost is a benefit when compared with scaling, it has also been identified as a challenge to the commercialization of 3D ICs in mainstream consumer applications. However, work is being done to address this. Although 3D technology is new and fairly complex, the cost of the manufacturing process is surprisingly straightforward when broken down into the activities that build up the entire process. By analyzing the combination of activities that lay at the base, cost drivers can be identified. Once the cost drivers are identified, it becomes a less complicated endeavor to determine where the majority of cost comes from and, more importantly, where cost has the potential to be reduced.
; Yield: Each extra manufacturing step adds a risk for defects. In order for 3D ICs to be commercially viable, defects could be repaired or tolerated, or defect density can be improved.
; Heat: Heat building up within the stack must be dissipated. This is an inevitable issue as electrical proximity correlates with thermal proximity. Specific thermal hotspots must be more carefully managed.
; Design complexity: Taking full advantage of 3D integration requires sophisticated design techniques and new
CAD
Computer-aided design (CAD) is the use of computers (or ) to aid in the creation, modification, analysis, or optimization of a design. This software is used to increase the productivity of the designer, improve the quality of design, improve co ...
tools.
; TSV-introduced overhead: TSVs are large compared to gates and impact floorplans. At the 45 nm technology node, the area footprint of a 10μm x 10μm TSV is comparable to that of about 50 gates.
Furthermore, manufacturability demands landing pads and keep-out zones which further increase TSV area footprint. Depending on the technology choices, TSVs block some subset of layout resources.
Via-first TSVs are manufactured before metallization, thus occupy the device layer and result in placement obstacles. Via-last TSVs are manufactured after metallization and pass through the chip. Thus, they occupy both the device and metal layers, resulting in placement and routing obstacles. While the usage of TSVs is generally expected to reduce wirelength, this depends on the number of TSVs and their characteristics.
Also, the granularity of inter-die partitioning impacts wirelength. It typically decreases for moderate (blocks with 20-100 modules) and coarse (block-level partitioning) granularities, but increases for fine (gate-level partitioning) granularities.
; Testing: To achieve high overall yield and reduce costs, separate testing of independent dies is essential.
However, tight integration between adjacent active layers in 3D ICs entails a significant amount of interconnect between different sections of the same circuit module that were partitioned to different dies. Aside from the massive overhead introduced by required TSVs, sections of such a module, e.g., a multiplier, cannot be independently tested by conventional techniques. This particularly applies to timing-critical paths laid out in 3D.
; Lack of standards: There are few standards for TSV-based 3D IC design, manufacturing, and packaging, although this issue is being addressed.
In addition, there are many integration options being explored such as via-last, via-first, via-middle;
interposers
or direct bonding; etc.
; Heterogeneous integration supply chain: In heterogeneously integrated systems, the delay of one part from one of the different parts suppliers delays the delivery of the whole product, and so delays the revenue for each of the 3D IC part suppliers.
; Lack of clearly defined ownership: It is unclear who should own the 3D IC integration and packaging/assembly. It could be assembly houses like
ASE
Ase may refer to:
* Ase, Nigeria, a town in Delta State, Nigeria
* -ase, a suffix used for the names of enzymes
* Aṣẹ, a West African philosophical concept
* American Sign Language (ISO 639-3 code: ase)
See also
* Åse (disambiguation)
* ...
or the product
OEM
An original equipment manufacturer (OEM) is generally perceived as a company that produces non-aftermarket parts and equipment that may be marketed by another manufacturer. It is a common industry term recognized and used by many professional or ...
s.
Design styles
Depending on partitioning granularity, different design styles can be distinguished. Gate-level integration faces multiple challenges and currently appears less practical than block-level integration.
; Gate-level integration: This style partitions standard cells between multiple dies. It promises wirelength reduction and great flexibility. However, wirelength reduction may be undermined unless modules of certain minimal size are preserved. On the other hand, its adverse effects include the massive number of necessary TSVs for interconnects. This design style requires 3D
place-and-route tools, which are unavailable yet. Also, partitioning a design block across multiple dies implies that it cannot be fully
tested
''Tested'' is a live album by punk rock band Bad Religion. It was recorded in the USA, Canada, Germany, Estonia, Denmark, Italy and Austria, in 1996, and released in 1997. It is Bad Religion's second live album. Instead of using crowd microphon ...
before die stacking. After die stacking (post-bond testing), a single failed die can render several good dies unusable, undermining yield. This style also amplifies the impact of
process variation
Natural process variation, sometimes just called process variation, is the statistical description of natural fluctuations in process outputs.
Equations
The following equations are used for an ''x''-bar-control chart:
:\bar x = \sum_^n x_i/ ...
, especially inter-die variation. In fact, a 3D layout may yield more poorly than the same circuit laid out in 2D, contrary to the original promise of 3D IC integration.
Furthermore, this design style requires to redesign available Intellectual Property, since existing
IP blocks and EDA tools do not provision for 3D integration.
; Block-level integration: This style assigns entire design blocks to separate dies. Design blocks subsume most of the
netlist
In electronic design, a netlist is a description of the connectivity of an electronic circuit. In its simplest form, a netlist consists of a list of the electronic components in a circuit and a list of the nodes they are connected to. A network ...
connectivity and are linked by a small number of global interconnects. Therefore, block-level integration promises to reduce TSV overhead. Sophisticated 3D systems combining heterogeneous dies require distinct manufacturing processes at different technology nodes for fast and low-power random logic, several memory types, analog and RF circuits, etc. Block-level integration, which allows separate and optimized manufacturing processes, thus appears crucial for 3D integration. Furthermore, this style might facilitate the transition from current 2D design towards 3D IC design. Basically, 3D-aware tools are only needed for partitioning and thermal analysis.
Separate dies will be designed using (adapted) 2D tools and 2D blocks. This is motivated by the broad availability of reliable IP blocks. It is more convenient to use available 2D IP blocks and to place the mandatory TSVs in the unoccupied space between blocks instead of redesigning IP blocks and embedding TSVs.
Design-for-testability structures are a key component of IP blocks and can therefore be used to facilitate testing for 3D ICs. Also, critical paths can be mostly embedded within 2D blocks, which limits the impact of TSV and inter-die variation on manufacturing yield. Finally, modern chip design often requires
last-minute engineering changes. Restricting the impact of such changes to single dies is essential to limit cost.
History
Several years after the
MOS integrated circuit
upright=1.6, gate (G), body (B), source (S), and drain (D) terminals. The gate is separated from the body by an gate oxide">insulating layer (pink).
The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET), also ...
(MOS IC) chip was first proposed by
Mohamed Atalla at
Bell Labs
Nokia Bell Labs, originally named Bell Telephone Laboratories (1925–1984),
then AT&T Bell Laboratories (1984–1996)
and Bell Labs Innovations (1996–2007),
is an American industrial Research and development, research and scientific developm ...
in 1960,
the concept of a three-dimensional MOS integrated circuit was proposed by
Texas Instruments
Texas Instruments Incorporated (TI) is an American technology company headquartered in Dallas, Texas, that designs and manufactures semiconductors and various integrated circuits, which it sells to electronics designers and manufacturers globa ...
researchers Robert W. Haisty, Rowland E. Johnson and Edward W. Mehal in 1964. In 1969, the concept of a three-dimensional MOS integrated circuit
memory chip
Semiconductor memory is a digital electronic semiconductor device used for digital data storage, such as computer memory. It typically refers to devices in which data is stored within metal–oxide–semiconductor (MOS) memory cells on a sil ...
was proposed by
NEC
is a Japanese multinational information technology and electronics corporation, headquartered in Minato, Tokyo. The company was known as the Nippon Electric Company, Limited, before rebranding in 1983 as NEC. It provides IT and network soluti ...
researchers Katsuhiro Onoda, Ryo Igarashi, Toshio Wada, Sho Nakanuma and Toru Tsujide.
Arm has made a high-density 3D logic test chip, and Intel with its Foveros 3D logic chip packing is planning to ship CPUs using it.
Demonstrations (19832012)
Japan (19832005)
3D ICs were first successfully demonstrated in
1980s Japan, where
research and development (R&D) on 3D ICs was initiated in 1981 with the "Three Dimensional Circuit Element R&D Project" by the Research and Development Association for Future (New) Electron Devices.
There were initially two forms of 3D IC design being investigated, recrystallization and
wafer bonding
Wafer bonding is a packaging technology on wafer-level for the fabrication of microelectromechanical systems (MEMS), nanoelectromechanical systems (NEMS), microelectronics and optoelectronics, ensuring a mechanically stable and hermetically sealed ...
, with the earliest successful demonstrations using recrystallization.
In October 1983, a
Fujitsu research team including S. Kawamura, Nobuo Sasaki and T. Iwai successfully
fabricated a three-dimensional
complementary metal-oxide-semiconductor (CMOS) integrated circuit, using laser beam recrystallization. It consisted of a structure in which one type of
transistor
upright=1.4, gate (G), body (B), source (S) and drain (D) terminals. The gate is separated from the body by an insulating layer (pink).
A transistor is a semiconductor device used to Electronic amplifier, amplify or electronic switch, switch ...
is fabricated directly above a transistor of the opposite type, with separate gates and an insulator in between. A double-layer of
silicon nitride
Silicon nitride is a chemical compound of the elements silicon and nitrogen. is the most thermodynamically stable and commercially important of the silicon nitrides, and the term "silicon nitride" commonly refers to this specific composition. It ...
and
phosphosilicate glass (PSG) film was used as an intermediate insulating layer between the top and bottom devices. This provided the basis for realizing a multi-layered 3D device composed of vertically-stacked transistors, with separate gates and an insulating layer in between. In December 1983, the same Fujitsu research team fabricated a 3D integrated circuit with a
silicon-on-insulator (SOI) CMOS structure. The following year, they fabricated a 3D
gate array
A gate array is an approach to the design and manufacture of application-specific integrated circuits (ASICs) using a prefabricated chip with components that are later interconnected into logic devices (e.g. NAND gates, flip-flops, etc.) according ...
with vertically-stacked dual SOI/CMOS structure using beam recrystallization.
In 1986,
Mitsubishi Electric researchers Yoichi Akasaka and Tadashi Nishimura laid out the basic concepts and proposed technologies for 3D ICs.
The following year, a Mitsubishi research team including Nishimura, Akasaka and
Osaka University graduate Yasuo Inoue fabricated an
image signal processor (ISP) on a 3D IC, with an array of
photosensors
Photodetectors, also called photosensors, are sensors of light or other electromagnetic radiation. There is a wide variety of photodetectors which may be classified by mechanism of detection, such as photoelectric or photochemical effects, or by ...
, CMOS
A-to-D converter
In electronics, an analog-to-digital converter (ADC, A/D, or A-to-D) is a system that converts an analog signal, such as a sound picked up by a microphone or light entering a digital camera, into a digital signal. An ADC may also provid ...
s,
arithmetic logic units (ALU) and
shift registers
A shift register is a type of digital circuit using a cascade of flip-flops where the output of one flip-flop is connected to the input of the next. They share a single clock signal, which causes the data stored in the system to shift from one lo ...
arranged in a three-layer structure. In 1989, an
NEC
is a Japanese multinational information technology and electronics corporation, headquartered in Minato, Tokyo. The company was known as the Nippon Electric Company, Limited, before rebranding in 1983 as NEC. It provides IT and network soluti ...
research team led by Yoshihiro Hayashi fabricated a 3D IC with a four-layer structure using laser beam crystallisation.
In 1990, a
Matsushita research team including K. Yamazaki, Y. Itoh and A. Wada fabricated a
parallel
Parallel is a geometric term of location which may refer to:
Computing
* Parallel algorithm
* Parallel computing
* Parallel metaheuristic
* Parallel (software), a UNIX utility for running programs in parallel
* Parallel Sysplex, a cluster of ...
image signal processor on a four-layer 3D IC, with SOI (
silicon-on-insulator) layers formed by laser recrystallization, and the four layers consisting of an
optical sensor
A sensor is a device that produces an output signal for the purpose of sensing a physical phenomenon.
In the broadest definition, a sensor is a device, module, machine, or subsystem that detects events or changes in its environment and sends ...
, level detector,
memory
Memory is the faculty of the mind by which data or information is encoded, stored, and retrieved when needed. It is the retention of information over time for the purpose of influencing future action. If past events could not be remembered, ...
and ALU.
The most common form of 3D IC design is wafer bonding.
Wafer bonding was initially called "cumulatively bonded IC" (CUBIC), which began development in 1981 with the "Three Dimensional Circuit Element R&D Project" in Japan and was completed in 1990 by Yoshihiro Hayashi's NEC research team, who demonstrated a method where several
thin-film
A thin film is a layer of material ranging from fractions of a nanometer (monolayer) to several micrometers in thickness. The controlled synthesis of materials as thin films (a process referred to as deposition) is a fundamental step in many ap ...
devices are bonded cumulatively, which would allow a large number of device layers. They proposed fabrication of separate devices in separate wafers, reduction in the thickness of the wafers, providing front and back leads, and connecting the thinned
die
Die, as a verb, refers to death, the cessation of life.
Die may also refer to:
Games
* Die, singular of dice, small throwable objects used for producing random numbers
Manufacturing
* Die (integrated circuit), a rectangular piece of a semicondu ...
to each other. They used CUBIC technology to fabricate and test a two active layer device in a top-to-bottom fashion, having a bulk-Si
NMOS FET
The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is a type of field-effect transistor (FET), most commonly fabricated by the controlled oxidation of silicon. It has an insulated gate, the voltage of which d ...
lower layer and a thinned NMOS FET upper layer, and proposed CUBIC technology that could fabricate 3D ICs with more than three active layers.
The first 3D IC stacked chips fabricated with a
through-silicon via
In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high-performance interconnect techniques used as an alternative ...
(TSV) process were invented in 1980s Japan.
Hitachi
() is a Japanese multinational corporation, multinational Conglomerate (company), conglomerate corporation headquartered in Chiyoda, Tokyo, Japan. It is the parent company of the Hitachi Group (''Hitachi Gurūpu'') and had formed part of the Ni ...
filed a Japanese patent in 1983, followed by Fujitsu in 1984. In 1986, a Japanese patent filed by Fujitsu described a stacked chip structure using TSV.
In 1989, Mitsumasa Koyonagi of
Tohoku University
, or is a Japanese national university located in Sendai, Miyagi in the Tōhoku Region, Japan. It is informally referred to as . Established in 1907, it was the third Imperial University in Japan and among the first three Designated National ...
pioneered the technique of wafer-to-wafer bonding with TSV, which he used to fabricate a 3D
LSI chip in 1989.
In 1999, the Association of Super-Advanced Electronics Technologies (ASET) in Japan began funding the development of 3D IC chips using TSV technology, called the "R&D on High Density Electronic System Integration Technology" project.
The term "through-silicon via" (TSV) was coined by Tru-Si Technologies researchers Sergey Savastiouk, O. Siniaguine, and E. Korczynski, who proposed a TSV method for a 3D
wafer-level packaging
Wafer-level packaging (WLP) is a process where packaging components are attached to an integrated circuit (IC) ''before'' the wafer – on which the IC is fabricated – is diced. In WSP, the top and bottom layers of the packaging and the solder ...
(WLP) solution in 2000.
The Koyanagi Group at
Tohoku University
, or is a Japanese national university located in Sendai, Miyagi in the Tōhoku Region, Japan. It is informally referred to as . Established in 1907, it was the third Imperial University in Japan and among the first three Designated National ...
, led by Mitsumasa Koyanagi, used TSV technology to fabricate a three-layer
memory chip
Semiconductor memory is a digital electronic semiconductor device used for digital data storage, such as computer memory. It typically refers to devices in which data is stored within metal–oxide–semiconductor (MOS) memory cells on a sil ...
in 2000, a three-layer artificial retina chip in 2001, a three-layer
microprocessor
A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circu ...
in 2002, and a ten-layer memory chip in 2005.
The same year, a
Stanford University research team consisting of Kaustav Banerjee, Shukri J. Souri, Pawan Kapur and Krishna C. Saraswat presented a novel 3D chip design that exploits the vertical dimension to alleviate the interconnect related problems and facilitates heterogeneous integration of technologies to realize a
system-on-a-chip
A system on a chip or system-on-chip (SoC ; pl. ''SoCs'' ) is an integrated circuit that integrates most or all components of a computer or other electronic system. These components almost always include a central processing unit (CPU), memory ...
(SoC) design.
In 2001, a
Toshiba
, commonly known as Toshiba and stylized as TOSHIBA, is a Japanese multinational conglomerate corporation headquartered in Minato, Tokyo, Japan. Its diversified products and services include power, industrial and social infrastructure system ...
research team including T. Imoto, M. Matsui and C. Takubo developed a "System Block Module" wafer bonding process for manufacturing 3D IC packages.
Europe (19882005)
Fraunhofer and
Siemens
Siemens AG ( ) is a German multinational conglomerate corporation and the largest industrial manufacturing company in Europe headquartered in Munich with branch offices abroad.
The principal divisions of the corporation are ''Industry'', '' ...
began research on 3D IC integration in 1987.
In 1988, they fabricated 3D CMOS IC devices based on re-crystallization of poly-silicon. In 1997, the inter-chip via (ICV) method was developed by a FraunhoferSiemens research team including Peter Ramm, Manfred Engelhardt, Werner Pamler, Christof Landesberger and Armin Klumpp. It was a first industrial 3D IC process, based on Siemens CMOS fab wafers. A variation of that TSV process was later called TSV-SLID (solid liquid inter-diffusion) technology. It was an approach to 3D IC design based on low temperature wafer bonding and vertical integration of IC devices using inter-chip vias, which they patented.
Ramm went on to develop industry-academic consortia for production of relevant 3D integration technologies. In the German funded cooperative VIC project between Siemens and Fraunhofer, they demonstrated a complete industrial 3D IC stacking process (1993–1996). With his Siemens and Fraunhofer colleagues, Ramm published results showing the details of key processes such as 3D metallization
. Grassl, P. Ramm, M. Engelhardt, Z. Gabric, O. Spindler, First International Dielectrics for VLSI/ULSI Interconnection Metallization Conference – DUMIC, Santa Clara, CA, 20–22 Feb, 1995and at ECTC 1995 they presented early investigations on stacked memory in processors.
In the early 2000s, a team of Fraunhofer and Infineon Munich researchers investigated 3D TSV technologies with particular focus on die-to-substrate stacking within the German/Austrian EUREKA project VSI and initiated the European Integrating Projects e-CUBES, as a first European 3D technology platform, and e-BRAINS with a.o., Infineon, Siemens, EPFL, IMEC and Tyndall, where heterogeneous 3D integrated system demonstrators were fabricated and evaluated. A particular focus of the e-BRAINS project was the development of novel low-temperature processes for highly reliable 3D integrated sensor systems.
United States (19992012)
Copper-to-copper wafer bonding, also called Cu-Cu connections or Cu-Cu wafer bonding, was developed at
MIT
The Massachusetts Institute of Technology (MIT) is a private land-grant research university in Cambridge, Massachusetts. Established in 1861, MIT has played a key role in the development of modern technology and science, and is one of the m ...
by a research team consisting of Andy Fan, Adnan-ur Rahman and Rafael Reif in 1999.
Reif and Fan further investigated Cu-Cu wafer bonding with other MIT researchers including Kuan-Neng Chen, Shamik Das, Chuan Seng Tan and Nisha Checka during 20012002.
In 2003,
DARPA
The Defense Advanced Research Projects Agency (DARPA) is a research and development agency of the United States Department of Defense responsible for the development of emerging technologies for use by the military.
Originally known as the Ad ...
and the Microelectronics Center of North Carolina (MCNC) began funding R&D on 3D IC technology.
In 2004, Tezzaron Semiconductor built working 3D devices from six different designs.
The chips were built in two layers with "via-first" tungsten TSVs for vertical interconnection. Two wafers were stacked face-to-face and bonded with a copper process. The top wafer was thinned and the two-wafer stack was then diced into chips. The first chip tested was a simple memory register, but the most notable of the set was an 8051 processor/memory stack that exhibited much higher speed and lower power consumption than an analogous 2D assembly.
In 2004,
Intel
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the developers of the x86 seri ...
presented a 3D version of the
Pentium 4
Pentium 4 is a series of single-core CPUs for desktops, laptops and entry-level servers manufactured by Intel. The processors were shipped from November 20, 2000 until August 8, 2008. The production of Netburst processors was active from 2000 ...
CPU.
The chip was manufactured with two dies using face-to-face stacking, which allowed a dense via structure. Backside TSVs are used for I/O and power supply. For the 3D floorplan, designers manually arranged functional blocks in each die aiming for power reduction and performance improvement. Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspots. The 3D design provides 15% performance improvement (due to eliminated pipeline stages) and 15% power saving (due to eliminated repeaters and reduced wiring) compared to the 2D Pentium 4.
The
Teraflops Research Chip
Intel Teraflops Research Chip (codenamed ''Polaris'') is a research manycore processor containing 80 cores, using a network-on-chip architecture, developed by Intel's Tera-Scale Computing Research Program. It was manufactured using a 65 n ...
introduced in 2007 by Intel is an experimental 80-core design with stacked memory. Due to the high demand for memory bandwidth, a traditional I/O approach would consume 10 to 25 W.
To improve upon that, Intel designers implemented a TSV-based memory bus. Each core is connected to one memory tile in the
SRAM die with a link that provides 12 GB/s bandwidth, resulting in a total bandwidth of 1 TB/s while consuming only 2.2 W.
An academic implementation of a 3D processor was presented in 2008 at the
University of Rochester
The University of Rochester (U of R, UR, or U of Rochester) is a private research university in Rochester, New York. The university grants undergraduate and graduate degrees, including doctoral and professional degrees.
The University of Roc ...
by Professor Eby Friedman and his students. The chip runs at a 1.4 GHz and it was designed for optimized vertical processing between the stacked chips which gives the 3D processor abilities that the traditional one layered chip could not reach.
One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in harmony without any obstacles that would interfere with a piece of information traveling from one layer to another.
In ISSCC 2012, two 3D-IC-based multi-core designs using
GlobalFoundries
GlobalFoundries Inc. (GF or GloFo) is a multinational semiconductor contract manufacturing and design company incorporated in the Cayman Islands and headquartered in Malta, New York. Created by the divestiture of the manufacturing arm of AMD, th ...
' 130 nm process and Tezzaron's FaStack technology were presented and demonstrated:
* 3D-MAPS,
a 64 custom core implementation with two-logic-die stack, was demonstrated by researchers from the School of Electrical and Computer Engineering at
Georgia Institute of Technology
The Georgia Institute of Technology, commonly referred to as Georgia Tech or, in the state of Georgia, as Tech or The Institute, is a public research university and institute of technology in Atlanta, Georgia. Established in 1885, it is part of ...
.
* Centip3De, near-threshold design based on ARM Cortex-M3 cores, was from the Department of Electrical Engineering and Computer Science at
University of Michigan
, mottoeng = "Arts, Knowledge, Truth"
, former_names = Catholepistemiad, or University of Michigania (1817–1821)
, budget = $10.3 billion (2021)
, endowment = $17 billion (2021)As o ...
.
Commercial 3D ICs (2004present)
![Psp-1000](https://upload.wikimedia.org/wikipedia/commons/4/46/Psp-1000.jpg)
The earliest known commercial use of a 3D IC chip was in
Sony
, commonly stylized as SONY, is a Japanese multinational conglomerate corporation headquartered in Minato, Tokyo, Japan. As a major technology company, it operates as one of the world's largest manufacturers of consumer and professional ...
's
PlayStation Portable
The PlayStation Portable (PSP) is a handheld game console developed and marketed by Sony Computer Entertainment. It was first released in Japan on December 12, 2004, in North America on March 24, 2005, and in PAL regions on September 1, 2005, ...
(PSP)
handheld game console
A handheld game console, or simply handheld console, is a small, portable self-contained video game console with a built-in screen, game controls and speakers. Handheld game consoles are smaller than home video game consoles and contain the cons ...
, released in 2004. The
PSP hardware
The PlayStation Portable's hardware consists of the physical components of the PlayStation Portable (PSP) and its accessories.
Overview
The PSP was designed by for the Sony Computer Entertainment subsidiary of Sony Corporation. Early models pre- ...
includes
eDRAM
Embedded DRAM (eDRAM) is dynamic random-access memory (DRAM) integrated on the same die or multi-chip module (MCM) of an application-specific integrated circuit (ASIC) or microprocessor. eDRAM's cost-per-bit is higher when compared to equivalen ...
(embedded
DRAM)
memory
Memory is the faculty of the mind by which data or information is encoded, stored, and retrieved when needed. It is the retention of information over time for the purpose of influencing future action. If past events could not be remembered, ...
manufactured by
Toshiba
, commonly known as Toshiba and stylized as TOSHIBA, is a Japanese multinational conglomerate corporation headquartered in Minato, Tokyo, Japan. Its diversified products and services include power, industrial and social infrastructure system ...
in a 3D
system-in-package chip with two
dies stacked vertically.
Toshiba called it "semi-embedded DRAM" at the time, before later calling it a stacked "
chip-on-chip
ChIP-on-chip (also known as ChIP-chip) is a technology that combines chromatin immunoprecipitation ('ChIP') with DNA microarray (''"chip"''). Like regular ChIP, ChIP-on-chip is used to investigate interactions between proteins and DNA ''in vivo' ...
" (CoC) solution.
In April 2007, Toshiba commercialized an eight-layer 3D IC, the 16
GB THGAM
embedded NAND flash
Flash memory is an electronic non-volatile computer memory storage medium that can be electrically erased and reprogrammed. The two main types of flash memory, NOR flash and NAND flash, are named for the NOR and NAND logic gates. Both use ...
memory chip, which was manufactured with eight stacked 2GB NAND flash chips. In September 2007,
Hynix
SK hynix Inc. is a South Korean supplier of dynamic random-access memory (DRAM) chips and flash memory chips. Hynix is the world's second-largest memory chipmaker (after Samsung Electronics) and the world's third-largest semiconductor company. ...
introduced 24-layer 3D IC technology, with a 16GB flash memory chip that was manufactured with 24 stacked NAND flash chips using a wafer bonding process. Toshiba also used an eight-layer 3D IC for their 32GB THGBM flash chip in 2008. In 2010, Toshiba used a 16-layer 3D IC for their 128GB THGBM2 flash chip, which was manufactured with 16 stacked 8GB chips.
In the 2010s, 3D ICs came into widespread commercial use in the form of
multi-chip package
A multi-chip module (MCM) is generically an electronic assembly (such as a package with a number of conductor terminals or "pins") where multiple integrated circuits (ICs or "chips"), semiconductor dies and/or other discrete components are int ...
and
package on package
Package on a package (PoP) is an integrated circuit packaging method to vertically combine discrete logic and memory ball grid array (BGA) packages. Two or more packages are installed atop each other, i.e. stacked, with a standard interface to rout ...
solutions for
NAND flash
Flash memory is an electronic non-volatile computer memory storage medium that can be electrically erased and reprogrammed. The two main types of flash memory, NOR flash and NAND flash, are named for the NOR and NAND logic gates. Both use ...
memory in
mobile devices
A mobile device (or handheld computer) is a computer small enough to hold and operate in the hand. Mobile devices typically have a flat LCD or OLED screen, a touchscreen interface, and digital or physical buttons. They may also have a physical ...
.
Elpida Memory
Micron Memory Japan, K.K. is a Japanese subsidiary of Micron Technology. It was formerly known as established in 1999 that developed, designed, manufactured and sold dynamic random-access memory (DRAM) products. It was also a semiconductor fou ...
developed the first 8
GB DRAM chip (stacked with four
DDR3
Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth ("double data rate") interface, and has been in use since 2007. It is the higher-speed ...
SDRAM dies) in September 2009, and released it in June 2011.
TSMC
Taiwan Semiconductor Manufacturing Company Limited (TSMC; also called Taiwan Semiconductor) is a Taiwanese multinational corporation, multinational semiconductor contract manufacturing and design company. It is the world's most valuable semicon ...
announced plans for 3D IC production with TSV technology in January 2010.
In 2011,
SK Hynix
SK hynix Inc. is a South Korean supplier of dynamic random-access memory (DRAM) chips and flash memory chips. Hynix is the world's second-largest memory chipmaker (after Samsung Electronics) and the world's third-largest semiconductor company ...
introduced 16GB DDR3 SDRAM (
40nm class) using TSV technology,
Samsung Electronics
Samsung Electronics Co., Ltd. (, sometimes shortened to SEC and stylized as SΛMSUNG) is a South Korean multinational electronics corporation headquartered in Yeongtong-gu, Suwon, South Korea. It is the pinnacle of the Samsung chaebol, a ...
introduced 3D-stacked 32GB DDR3 (
30nm class) based on TSV in September, and then Samsung and
Micron Technology
Micron Technology, Inc. is an American producer of computer memory and computer data storage including dynamic random-access memory, flash memory, and USB flash drives. It is headquartered in Boise, Idaho. Its consumer products, including ...
announced TSV-based
Hybrid Memory Cube (HMC) technology in October.
High Bandwidth Memory
High Bandwidth Memory (HBM) is a high-speed computer memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM) initially from Samsung, AMD and SK Hynix. It is used in conjunction with high-performance graphics accelerator ...
(HBM), developed by Samsung,
AMD
Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. While it initially manufactur ...
, and SK Hynix, uses stacked chips and TSVs. The first HBM memory chip was manufactured by SK Hynix in 2013.
In January 2016,
Samsung Electronics
Samsung Electronics Co., Ltd. (, sometimes shortened to SEC and stylized as SΛMSUNG) is a South Korean multinational electronics corporation headquartered in Yeongtong-gu, Suwon, South Korea. It is the pinnacle of the Samsung chaebol, a ...
announced early mass production of
HBM2
High Bandwidth Memory (HBM) is a high-speed computer memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM) initially from Samsung, AMD and SK Hynix. It is used in conjunction with high-performance graphics accelerators ...
, at up to 8 GB per stack.
In 2017, Samsung Electronics combined 3D IC stacking with its 3D
V-NAND
Flash memory is an electronic non-volatile computer memory storage medium that can be electrically erased and reprogrammed. The two main types of flash memory, NOR flash and NAND flash, are named for the NOR and NAND logic gates. Both us ...
technology (based on
charge trap flash
Charge trap flash (CTF) is a semiconductor memory technology used in creating non-volatile NOR and NAND flash memory. It is a type of floating-gate MOSFET memory technology, but differs from the conventional floating-gate technology in that it use ...
technology), manufacturing its 512GB KLUFG8R1EM flash memory chip with eight stacked 64-layer V-NAND chips.
In 2019, Samsung produced a 1
TB flash chip with 16 stacked V-NAND dies.
As of 2018, Intel is considering the use of 3D ICs to improve performance. , 232-layer NAND, i.e. memory device, chips are made by Micron,
that previously in April 2019 were making 96-layer chips; and Toshiba made 96-layer devices in 2018.
See also
*
Charge trap flash
Charge trap flash (CTF) is a semiconductor memory technology used in creating non-volatile NOR and NAND flash memory. It is a type of floating-gate MOSFET memory technology, but differs from the conventional floating-gate technology in that it use ...
(CTF)
*
FinFET
A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal-oxide-semiconductor field-effect transistor) built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, f ...
(3D transistor)
*
MOSFET
The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is a type of field-effect transistor (FET), most commonly fabricated by the controlled oxidation of silicon. It has an insulated gate, the voltage of which d ...
*
Multigate device
A multigate device, multi-gate MOSFET or multi-gate field-effect transistor (MuGFET) refers to a metal–oxide–semiconductor field-effect transistor (MOSFET) that has more than one gate on a single transistor. The multiple gates may be control ...
(MuGFET)
*
V-NAND
Flash memory is an electronic non-volatile computer memory storage medium that can be electrically erased and reprogrammed. The two main types of flash memory, NOR flash and NAND flash, are named for the NOR and NAND logic gates. Both us ...
(3D NAND)
Notes
References
JEDECが「DDR4」とTSVを使う「3DS」メモリ技術の概要を明らかに- 後藤弘茂のWeekly海外ニュース Impress Watch Co. (issued:2011-11-08, 2011-11-08)
貫通電極を用いたチップ積層技術の開発(Japanese) oki technical review #211 Vol.74 #3 (issued:2007-10, 2011-11-08)
(Japanese) Akita Elpida Memory, inc (2011-11-08)
Further reading
* Philip Garrou, Christopher Bower, Peter Ramm: ''Handbook of 3D Integration, Technology and Applications of 3D Integrated Circuits'' Vol. 1 and Vol. 2, Wiley-VCH, Weinheim 2008, .
* Yuan Xie, Jason Cong, Sachin Sapatnekar: ''Three-Dimensional Integrated Circuit Design: Eda, Design And Microarchitectures'', Publisher: Springer, , , 978-1441907837, Publishing Date: Dec. 2009.
* Philip Garrou, Mitsumasa Koyanagi, Peter Ramm: ''Handbook of 3D Integration, 3D Process Technology'' Vol. 3, Wiley-VCH, Weinheim 2014, .
* Paul D. Franzon, Erik Jan Marinissen, Muhannad S. Bakir, Philip Garrou, Mitsumasa Koyanagi, Peter Ramm: Handbook of 3D Integration: "Design, Test, and Thermal Management of 3D Integrated Circuits", Vol. 4, Wiley-VCH, Weinheim 2019, .
External links
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
{{Electronic components
Integrated circuits
Semiconductor device fabrication
Packaging (microfabrication)
Emerging technologies
Japanese inventions
MOSFETs