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Bogomips
BogoMips (from "bogus" and MIPS) is a crude measurement of CPU speed made by the Linux kernel when it boots to calibrate an internal busy-loop. An often-quoted definition of the term is "the number of million times per second a processor can do absolutely nothing".Eric S Raymond, and Geoff Mackenzie, published on the Internet in the early 1990s, untraceable origin. BogoMips is a value that can be used to verify whether the processor in question is in the proper range of similar processors, i.e. BogoMips represents a processor's clock frequency as well as the potentially present CPU cache. It is not usable for performance comparisons among different CPUs. History In 1993, Lars Wirzenius posted a Usenet message explaining the reasons for its introduction in the Linux kernel on comp.os.linux: : .. : MIPS is short for Millions of Instructions Per Second. It is a measure for the computation speed of a processor. Like most such measures, it is more often abused than used properly ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Million Instructions Per Second
Instructions per second (IPS) is a measure of a computer's processor speed. For complex instruction set computers (CISCs), different instructions take different amounts of time, so the value measured depends on the instruction mix; even for comparing processors in the same family the IPS measurement can be problematic. Many reported IPS values have represented "peak" execution rates on artificial instruction sequences with few branches and no cache contention, whereas realistic workloads typically lead to significantly lower IPS values. Memory hierarchy also greatly affects processor performance, an issue barely considered in IPS calculations. Because of these problems, synthetic benchmarks such as Dhrystone are now generally used to estimate computer performance in commonly used applications, and raw IPS has fallen into disuse. The term is commonly used in association with a metric prefix (k, M, G, T, P, or E) to form kilo instructions per second (kIPS), million instructions p ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Busy-loop
In computer science and software engineering, busy-waiting, busy-looping or spinning is a technique in which a process repeatedly checks to see if a condition is true, such as whether keyboard input or a lock is available. Spinning can also be used to generate an arbitrary time delay, a technique that was necessary on systems that lacked a method of waiting a specific length of time. Processor speeds vary greatly from computer to computer, especially as some processors are designed to dynamically adjust speed based on current workload. Consequently, spinning as a time-delay technique can produce unpredictable or even inconsistent results on different systems unless code is included to determine the time a processor takes to execute a "do nothing" loop, or the looping code explicitly checks a real-time clock. In most cases spinning is considered an anti-pattern and should be avoided, as processor time that could be used to execute a different task is instead wasted on useless activ ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Intel P5
The Pentium (also referred to as P5, its microarchitecture, or i586) is a fifth generation, 32-bit x86 microprocessor that was introduced by Intel on March 22, 1993, as the very first CPU in the Pentium brand. It was instruction set compatible with the 80486 but was a new and very different microarchitecture design from previous iterations. The P5 Pentium was the first superscalar x86 microarchitecture and the world's first superscalar microprocessor to be in mass productionmeaning it generally executes at least 2 instructions per clock mainly because of a design-first dual integer pipeline design previously thought impossible to implement on a CISC microarchitecture. Additional features include a faster floating-point unit, wider data bus, separate code and data caches, and many other techniques and features to enhance performance and support security, encryption, and multiprocessing, for workstations and servers when compared to the next best previous industry standard proces ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Cyrix 6x86
The Cyrix 6x86 is a line of sixth-generation, 32-bit x86 microprocessors designed and released by Cyrix in 1995. Cyrix, being a fabless company, had the chips manufactured by IBM and SGS-Thomson. The 6x86 was made as a direct competitor to Intel's Pentium microprocessor line, and was pin compatible. During the 6x86's development, the majority of applications (office software as well as games) performed almost entirely integer operations. The designers foresaw that future applications would most likely maintain this instruction focus. So, to optimize the chip's performance for what they believed to be the most likely application of the CPU, the integer execution resources received most of the transistor budget. This would later prove to be a strategic mistake, as the popularity of the P5 Pentium caused many software developers to hand-optimize code in assembly language, to take advantage of the P5 Pentium's tightly pipelined and lower latency FPU. For example, the highly anticip ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Cyrix Cx5x86
The Cyrix 5x86 was a line of x86 microprocessors designed by Cyrix and released on June 5 of 1995. Cyrix, being a fabless company, had the chips manufactured by IBM. The line came out about 5 months before the more famous Cyrix 6x86. The Cyrix 5x86 was one of the fastest CPUs ever produced for Socket 3 computer systems. With better performance in most applications than an Intel Pentium processor at 75 MHz, the Cyrix Cx5x86 filled a gap by providing a medium-performance processor option for 486 Socket 3 motherboards (which are incapable of handling Intel's Pentium CPUs, apart from the Pentium Overdrive). The IBM 5x86C is an IBM branded and produced version of the Cyrix-designed Cyrix Cx5x86 CPU. Previous IBM x86 processors, IBM 386SLC and IBM 486SLC, were based on modified Intel designs. Design The Cyrix 5x86 processor, codename "M1sc", was based on a scaled-down version of the "M1" core used in the Cyrix 6x86, which provided 80% of the performance for a 50% decrea ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Pentium Pro
The Pentium Pro is a sixth-generation x86 microprocessor developed and manufactured by Intel and introduced on November 1, 1995. It introduced the P6 microarchitecture (sometimes termed i686) and was originally intended to replace the original Pentium in a full range of applications. While the Pentium and Pentium MMX had 3.1 and 4.5 million transistors, respectively, the Pentium Pro contained 5.5 million transistors. Later, it was reduced to a more narrow role as a server and high-end desktop processor and was used in supercomputers like ASCI Red, the first computer to reach the trillion ''floating point operations per second'' (teraFLOPS) performance mark. The Pentium Pro was capable of both dual- and quad-processor configurations. It only came in one form factor, the relatively large rectangular Socket 8. The Pentium Pro was succeeded by the Pentium II Xeon in 1998. Microarchitecture The lead architect of Pentium Pro was Fred Pollack who was specialized in supe ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Alpha 21164
The Alpha 21164, also known by its code name, EV5, is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented the Alpha instruction set architecture (ISA). It was introduced in January 1995, succeeding the Alpha 21064A as Digital's flagship microprocessor. It was succeeded by the Alpha 21264 in 1998. History First silicon of the Alpha 21164 was produced in February 1994, and the OpenVMS, Digital UNIX and Windows NT operating systems were successfully booted on it. It was sampled in late 1994 and was introduced in January 1995 at 266 MHz. A 300 MHz version was introduced in March 1995. The final Alpha 21164, a 333 MHz version, was announced on 2 October 1995, available in sample quantities. The Alpha 21164 was replaced by the Alpha 21164A as Digital's flagship microprocessor in 1996 when a 400 MHz version became available in volume quantities. Users Digital used the Alpha 21164 operating at various clock frequencies in their ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Alpha 21064
The Alpha 21064 is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented the Alpha (introduced as the Alpha AXP) instruction set architecture (ISA). It was introduced as the DECchip 21064 before it was renamed in 1994. The 21064 is also known by its code name, EV4. It was announced in February 1992 with volume availability in September 1992. The 21064 was the first commercial implementation of the Alpha ISA, and the first microprocessor from Digital to be available commercially. It was succeeded by a derivative, the Alpha 21064A in October 1993. This last version was replaced by the Alpha 21164 in 1995. History The first Alpha processor was a test chip codenamed EV3. This test chip was fabricated using Digital's 1.0-micrometre (μm) CMOS-3 process. The test chip lacked a floating point unit and only had 1 KB caches. The test chip was used to confirm the operation of the aggressive circuit design techniques. The test chip, along with sim ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
NexGen
NexGen (Milpitas, California) was a private semiconductor company that designed x86 microprocessors until it was purchased by AMD in 1996. NexGen was a fabless design house that designed its chips but relied on other companies for production. NexGen's chips were produced by IBM's Microelectronics division in Burlington, Vermont alongside PowerPC and DRAM parts. The company was best known for the unique implementation of the x86 architecture in its processors. NexGen's CPUs were designed very differently from other processors based on the x86 instruction set at the time: the processor would translate code designed to run on the traditionally CISC-based x86 architecture to run on the chip's internal RISC architecture. The architecture was used in later AMD chips such as the K6, and to an extent most x86 processors today implement a "hybrid" architecture similar to those used in NexGen's processors. It went public in 1994, and was bought by AMD in 1995 for $850M. The technology ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
StrongARM
The StrongARM is a family of computer microprocessors developed by Digital Equipment Corporation and manufactured in the late 1990s which implemented the ARM v4 instruction set architecture. It was later acquired by Intel in 1997 from DEC's own Digital Semiconductor division as part of a settlement of a lawsuit between the two companies over plagiarism. Intel then continued to manufacture it before replacing it with the StrongARM-derived ARM-based follow-up architecture called XScale in the early 2000s. History According to Allen Baum, the StrongARM traces its history to attempts to make a low-power version of the DEC Alpha, which DEC's engineers quickly concluded was not possible. They then became interested in designs dedicated to low-power applications which led them to the ARM family. One of the only major users of the ARM for performance-related products at that time was Apple, whose Newton device was based on the ARM platform. DEC approached Apple wondering if they migh ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
PowerPC
PowerPC (with the backronym Performance Optimization With Enhanced RISC – Performance Computing, sometimes abbreviated as PPC) is a reduced instruction set computer (RISC) instruction set architecture (ISA) created by the 1991 Apple Inc., Apple–IBM–Motorola alliance, known as AIM alliance, AIM. PowerPC, as an evolving instruction set, has been named Power ISA since 2006, while the old name lives on as a trademark for some implementations of Power Architecture–based processors. PowerPC was the cornerstone of AIM's PReP and Common Hardware Reference Platform (CHRP) initiatives in the 1990s. Originally intended for personal computers, the architecture is well known for being used by Apple's Power Macintosh, PowerBook, iMac, iBook, eMac, Mac Mini, and Xserve lines from 1994 until 2005, when Mac transition to Intel processors, Apple migrated to Intel's x86. It has since become a niche in personal computers, but remains popular for embedded system, embedded and high-performanc ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Motorola 68040
The Motorola 68040 ("''sixty-eight-oh-forty''") is a 32-bit microprocessor in the Motorola 68000 series, released in 1990. It is the successor to the 68030 and is followed by the 68060, skipping the 68050. In keeping with general Motorola naming, the 68040 is often referred to as simply the '040 (pronounced ''oh-four-oh'' or ''oh-forty''). The 68040 was the first 680x0 family member with an on-chip Floating-Point Unit (FPU). It thus included all of the functionality that previously required external chips, namely the FPU and Memory Management Unit (MMU), which was added in the 68030. It also had split instruction and data caches of 4 kilobytes each. It was fully pipelined, with six stages. Versions of the 68040 were created for specific market segments, including the 68LC040, which removed the FPU, and the 68EC040, which removed both the FPU and MMU. Motorola had intended the EC variant for embedded use, but embedded processors during the 68040's time did not need the powe ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
