ARM9

ARM9 is a group of 32-bit RISC ARM processor cores licensed by ARM Holdings for microcontroller use.ARM9 Family Webpage; ARM Holdings.
/ref> The ARM9 core family consists of ARM9TDMI, ARM940T, ARM9E-S, ARM966E-S, ARM920T, ARM922T, ARM946E-S, ARM9EJ-S, ARM926EJ-S, ARM968E-S, ARM996HS. Since ARM9 cores were released from 1998 to 2006, they are no longer recommended for new IC designs, instead ARM Cortex-A, ARM Cortex-M, ARM Cortex-R cores are preferred.

Overview

With this design generation, ARM moved from a von Neumann architecture (Princeton architecture) to a (modified; meaning split cache) Harvard architecture with separate instruction and data buses (and caches), significantly increasing its potential speed. Most silicon chips integrating these cores will package them as modified Harvard architecture chips, combining the two address buses on the other side of separated CPU caches and tightly coupled memories.

There are two subfamilies, implementing different ARM architecture versions.

Differences from ARM7 cores

Key improvements over ARM7 cores, enabled by spending more transistors, include:

* Decreased heat production and lower overheating risk.
* Clock frequency improvements. Shifting from a three-stage pipeline to a five-stage one lets the clock speed be approximately doubled, on the same silicon fabrication process.
* Cycle count improvements. Many unmodified ARM7 binaries were measured as taking about 30% fewer cycles to execute on ARM9 cores. Key improvements include:
** Faster loads and stores; many instructions now cost just one cycle. This is helped by both the modified Harvard architecture (reducing bus and cache contention) and the new pipeline stages.
** Exposing pipeline interlocks, enabling compiler optimizations to reduce blockage between stages.

Additionally, some ARM9 cores incorporate "Enhanced DSP" instructions, such as a multiply-accumulate, to support more efficient implementations of digital signal processing algorithms.

Switching from a von Neumann architecture entailed using a non-unified cache, so that instruction fetches do not evict data (and vice versa). ARM9 cores have separate data and address bus signals, which chip designers use in various ways. In most cases they connect at least part of the address space in von Neumann style, used for both instructions and data, usually to an AHB interconnect connecting to a DRAM interface and an External Bus Interface usable with NOR flash memory. Such hybrids are no longer pure Harvard architecture processors.

ARM license

ARM Holdings neither manufactures nor sells CPU devices based on its own designs, but rather licenses the processor architecture to interested parties. ARM offers a variety of licensing terms, varying in cost and deliverables. To all licensees, ARM provides an integratable hardware description of the ARM core, as well as complete software development toolset and the right to sell manufactured silicon containing the ARM CPU.

Silicon customization

Integrated device manufacturers (IDM) receive the ARM Processor IP as synthesizable RTL (written in Verilog). In this form, they have the ability to perform architectural level optimizations and extensions. This allows the manufacturer to achieve custom design goals, such as higher clock speed, very low power consumption, instruction set extensions, optimizations for size, debug support, etc. To determine which components have been included in a particular ARM CPU chip, consult the manufacturer datasheet and related documentation.

Cores

The ARM MPCore family of multicore processors support software written using either the asymmetric (AMP) or symmetric ( SMP) multiprocessor programming paradigms. For AMP development, each central processing unit within the MPCore may be viewed as an independent processor and as such can follow traditional single processor development strategies.

ARM9TDMI

ARM9TDMI is a successor to the popular ARM7TDMI core, and is also based on the ARMv4T architecture. Cores based on it support both 32-bit ARM and 16-bit Thumb instruction sets and include:
* ARM920T with 16 KB each of I/D cache and an MMU
* ARM922T with 8 KB each of I/D cache and an MMU
* ARM940T with cache and a Memory Protection Unit (MPU)

ARM9E-S and ARM9EJ-S

ARM9E, and its ARM9EJ sibling, implement the basic ARM9TDMI pipeline, but add support for the ARMv5TE architecture, which includes some DSP-esque instruction set extensions. In addition, the multiplier unit width has been doubled, halving the time required for most multiplication operations. They support 32-bit, 16-bit, and sometimes 8-bit instruction sets.
* ARM926EJ-S with ARM Jazelle technology, which enables the direct execution of 8-bit Java bytecode in hardware, and an MMU
* ARM946
* ARM966
* ARM968
The TI-Nspire CX (2011) and CX II (2019) graphing calculators use an ARM926EJ-S processor, clocked at 132 and 396 MHz respectively.

Chips

;ARM920T
* Samsung S3C2440
* Atmel AT91RM9200Atmel Legacy ARM-Based Solutions; Atmel.
/ref>

;ARM926EJ-S
* Cypress Semiconductor EZ-USB FX3
* Microchip Technology (former Atmel) AT91SAM9260, AT91SAM9G, AT91SAM9M, AT91SAM9N/CN, AT91SAM9R/RL, AT91SAM9X, AT91SAM9XE (see AT91SAM9)
* Nintendo Starlet ( Wii coprocessor)
* NXP (former Freescale Semiconductor) i.MX2 Series, (see I.MX), LPC3100 and LPC3200 Series
* Texas Instruments OMAP 850, 750, 733, 730, L137, L138, 5912 (also 5948, which is a customer specific version of it, made for Bosch)
* HP iLO 4 baseboard management controller
*5V Technologies 5VT1310/1312/1314
* STMicroelectronics SPEAr300/600
* VIA WonderMedia 8505 and 8650

;ARM940T
* Conexant CX22490 STB SoC

;ARM946E-S
* Nintendo NTR-CPU ( Nintendo DS CPU), TWL-CPU (Nintendo DSi CPU; same as the DS but clocked at 133 MHz instead of 67 MHz)

;ARM966E-S
* STMicroelectronics STR9

;Unreferenced ARM9 core
* ASPEED AST2400
* Atmel AT91CAP9
* CSR Quatro 4300
* Centrality Atlas III
* Cirrus Logic EP9315 ARM9 CPU, 200 MHz
* Digi NS9215, NS9210
* HiSilicon Kirin K3V1
* Infineon Technologies S-GOLDlite PMB 8875
* LeapFrog

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