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PowerPC
PowerPC
(with the backronym Performance Optimization With Enhanced RISC
RISC
– Performance Computing, sometimes abbreviated as PPC) is a reduced instruction set computing (RISC) instruction set architecture (ISA) created by the 1991 Apple–IBM– Motorola
Motorola
alliance, known as AIM. PowerPC, as an evolving instruction set, has since 2006 been named Power ISA, while the old name lives on as a trademark for some implementations of Power Architecture-based processors. PowerPC
PowerPC
was the cornerstone of AIM's PReP
PReP
and Common Hardware Reference Platform initiatives in the 1990s. Originally intended for personal computers, the architecture is well known for being used by Apple's Power Macintosh, PowerBook, iMac, iBook, and Xserve
Xserve
lines from 1994 until 2006, when Apple migrated to Intel's x86. It has since become niche in personal computers, but remain popular as embedded and high-performance processors. Its use in video game consoles and embedded applications provided an array of uses. In addition, PowerPC CPUs are still used in AmigaOne
AmigaOne
and third party AmigaOS 4
AmigaOS 4
personal computers. PowerPC
PowerPC
is largely based on IBM's earlier POWER instruction set architecture, and retains a high level of compatibility with it; the architectures have remained close enough that the same programs and operating systems will run on both if some care is taken in preparation; newer chips in the POWER series use the Power ISA.

Contents

1 History

1.1 Apple and Motorola
Motorola
involvement 1.2 Operating systems 1.3 Breakup of AIM 1.4 Generations

2 Design features

2.1 Endian modes

3 Implementations 4 Operating systems

4.1 Operating systems with native support 4.2 Embedded

5 Licensees

5.1 32-bit
32-bit
PowerPC 5.2 64-bit PowerPC 5.3 Game consoles 5.4 Desktop computers 5.5 Embedded applications

6 See also 7 References 8 Further reading 9 External links

History[edit] The history of RISC
RISC
began with IBM's 801 research project, on which John Cocke was the lead developer, where he developed the concepts of RISC
RISC
in 1975–78. 801-based microprocessors were used in a number of IBM
IBM
embedded products, eventually becoming the 16-register ROMP processor used in the IBM
IBM
RT. The RT was a rapid design implementing the RISC
RISC
architecture. Between the years of 1982–1984, IBM
IBM
started a project to build the fastest microprocessor on the market; this new 32-bit
32-bit
architecture became referred to as the America Project throughout its development cycle, which lasted for approximately 5–6 years. The result is the POWER instruction set architecture, introduced with the RISC
RISC
System/6000 in early 1990. The original POWER microprocessor, one of the first superscalar RISC implementations, is a high performance, multi-chip design. IBM
IBM
soon realized that a single-chip microprocessor was needed in order to scale its RS/6000
RS/6000
line from lower-end to high-end machines. Work began on a one-chip POWER microprocessor, designated the RSC ( RISC
RISC
Single Chip). In early 1991, IBM
IBM
realized its design could potentially become a high-volume microprocessor used across the industry. Apple and Motorola
Motorola
involvement[edit] Apple had already realized the limitations and risks of its dependency upon a single CPU vendor at a time when Motorola
Motorola
was falling behind on delivering the 68040 CPU. Furthermore, Apple had conducted its own research and made an experimental quad-core CPU design called Aquarius,[1]:86-90 which convinced the company's technology leadership that the future of computing was in the RISC
RISC
methodology.[1]:287-288 IBM
IBM
approached Apple with the goal of collaborating on the development of a family of single-chip microprocessors based on the POWER architecture. Soon after, Apple, being one of Motorola's largest customers of desktop-class microprocessors,[2] asked Motorola
Motorola
to join the discussions due to their long relationship, Motorola
Motorola
having had more extensive experience with manufacturing high-volume microprocessors than IBM, and to form a second source for the microprocessors. This three-way collaboration between Apple, IBM, and Motorola
Motorola
became known as the AIM alliance. In 1991, the PowerPC
PowerPC
was just one facet of a larger alliance among these three companies. At the time, most of the personal computer industry was shipping systems based on the Intel
Intel
80386 and 80486 chips, which have a complex instruction set computer (CISC) architecture, and development of the Pentium processor was well underway. The PowerPC
PowerPC
chip was one of several joint ventures involving the three alliance members, in their efforts to counter the growing Microsoft- Intel
Intel
dominance of personal computing. For Motorola, POWER looked like an unbelievable deal. It allowed the company to sell a widely tested and powerful RISC
RISC
CPU for little design cash on its own part. It also maintained ties with an important customer, Apple, and seemed to offer the possibility of adding IBM too, which might buy smaller versions from Motorola
Motorola
instead of making its own. At this point Motorola
Motorola
already had its own RISC
RISC
design in the form of the 88000, which was doing poorly in the market. Motorola
Motorola
was doing well with its 68000 family and the majority of the funding was focused on this. The 88000
88000
effort was somewhat starved for resources. The 88000
88000
was already in production, however; Data General
Data General
was shipping 88000
88000
machines and Apple already had 88000
88000
prototype machines running. The 88000
88000
had also achieved a number of embedded design wins in telecom applications. If the new POWER one-chip version could be made bus-compatible at a hardware level with the 88000, that would allow both Apple and Motorola
Motorola
to bring machines to market far faster since they would not have to redesign their board architecture. The result of these various requirements is the PowerPC
PowerPC
(performance computing) specification. The differences between the earlier POWER instruction set and that of PowerPC
PowerPC
is outlined in Appendix E of the manual for PowerPC
PowerPC
ISA v.2.02.[3] Operating systems[edit] Since 1991, IBM
IBM
had a long-standing desire for a unifying operating system that would simultaneously host all existing operating systems as personalities upon one microkernel. From 1991 to 1995, the company designed and aggressively evangelized what would become Workplace OS, primarily targeting PowerPC.[1]:290-291 When the first PowerPC
PowerPC
products reached the market, they were met with enthusiasm. In addition to Apple, both IBM
IBM
and the Motorola
Motorola
Computer Group offered systems built around the processors. Microsoft
Microsoft
released Windows NT 3.51
Windows NT 3.51
for the architecture, which was used in Motorola's PowerPC
PowerPC
servers, and Sun Microsystems
Sun Microsystems
offered a version of its Solaris OS. IBM
IBM
ported its AIX
AIX
Unix. Workplace OS featured a new port of OS/2 (with Intel
Intel
emulation for application compatibility), pending a successful launch of the PowerPC
PowerPC
620. Throughout the mid-1990s, PowerPC
PowerPC
processors achieved benchmark test scores that matched or exceeded those of the fastest x86 CPUs. Ultimately, demand for the new architecture on the desktop never truly materialized. Windows, OS/2, and Sun customers, faced with the lack of application software for the PowerPC, almost universally ignored the chip. IBM's Workplace OS platform (and thus, OS/2
OS/2
for PowerPC) was summarily canceled upon its first developers' release in December 1995 due to the simultaneous buggy launch of the PowerPC
PowerPC
620. The PowerPC versions of Solaris and Windows were discontinued after only a brief period on the market. Only on the Macintosh, due to Apple's persistence, did the PowerPC
PowerPC
gain traction. To Apple, the performance of the PowerPC
PowerPC
was a bright spot in the face of increased competition from Windows 95 and Windows NT-based PCs. With the cancellation of Workplace OS, the general PowerPC
PowerPC
platform (especially AIM's Common Hardware Reference Platform) was instead seen as a hardware-only compromise to run many operating systems one at a time upon a single unifying vendor-neutral hardware platform.[1]:287-288 In parallel with the alliance between IBM
IBM
and Motorola, both companies had development efforts underway internally. The PowerQUICC
PowerQUICC
line was the result of this work inside Motorola. The 4xx series of embedded processors was underway inside IBM. The IBM
IBM
embedded processor business grew to nearly US$100 million in revenue and attracted hundreds of customers.

The development of the PowerPC
PowerPC
is centered at an Austin, Texas, facility called the Somerset Design Center. The building is named after the site in Arthurian legend where warring forces put aside their swords, and members of the three teams that staff the building say the spirit that inspired the name has been a key factor in the project's success thus far. — MacWeek[4]

Part of the culture here is not to have an IBM
IBM
or Motorola
Motorola
or Apple culture, but to have our own. — Motorola's Russell Stanphill, codirector of Somerset[4]

Breakup of AIM[edit] Toward the close of the decade, manufacturing issues began plaguing the AIM alliance in much the same way they did Motorola, which consistently pushed back deployments of new processors for Apple and other vendors: first from Motorola
Motorola
in the 1990s with the PowerPC
PowerPC
7xx and 74xx processors, and IBM
IBM
with the 64-bit PowerPC 970
PowerPC 970
processor in 2003. In 2004, Motorola
Motorola
exited the chip manufacturing business by spinning off its semiconductor business as an independent company called Freescale Semiconductor. Around the same time, IBM
IBM
exited the 32-bit
32-bit
embedded processor market by selling its line of PowerPC products to Applied Micro Circuits Corporation
Applied Micro Circuits Corporation
(AMCC) and focusing on 64-bit chip designs, while maintaining its commitment of PowerPC
PowerPC
CPUs toward game console makers such as Nintendo's GameCube
GameCube
and Wii, Sony's PlayStation 3
PlayStation 3
and Microsoft's Xbox 360, of which the latter two both use 64-bit processors. In 2005 Apple announced they would no longer use PowerPC
PowerPC
processors in their Apple Macintosh computers, favoring Intel-produced processors instead, citing the performance limitations of the chip for future personal computer hardware specifically related to heat generation and energy usage, as well as the inability of IBM to move the 970 processor to the 3 GHz range. The IBM-Freescale alliance was replaced by an open standards body called Power.org. Power.org operates under the governance of the IEEE with IBM continuing to use and evolve the PowerPC
PowerPC
processor on game consoles and Freescale Semiconductor
Freescale Semiconductor
focusing solely on embedded devices.

A schematic showing the evolution of the different POWER, PowerPC
PowerPC
and Power ISAs

IBM
IBM
continues to develop PowerPC
PowerPC
microprocessor cores for use in their application-specific integrated circuit (ASIC) offerings. Many high volume applications embed PowerPC
PowerPC
cores. The PowerPC
PowerPC
specification is now handled by Power.org where IBM, Freescale, and AMCC are members. PowerPC, Cell and POWER processors are now jointly marketed as the Power Architecture. Power.org released a unified ISA, combining POWER and PowerPC
PowerPC
ISAs into the new Power ISA v.2.03 specification and a new reference platform for servers called PAPR ( Power Architecture
Power Architecture
Platform Reference). As of 2015[update], IBM's POWER microprocessors, which implement the Power ISA, are used by IBM
IBM
in their IBM
IBM
Power Systems, running IBM
IBM
i, AIX, and Linux. Generations[edit] Many PowerPC
PowerPC
designs are named and labeled by their apparent technology generation. That began with the "G3", which was an internal project name inside AIM for the development of what would become the PowerPC
PowerPC
750 family.[5] Apple popularized the term "G3" when they introduced Power Mac G3 and PowerBook
PowerBook
G3 at an event at 10 November 1997. Motorola
Motorola
and Apple liked the moniker and used the term "G4" for the 7400 family introduced in 1998[6][7] and the Power Mac G4
Power Mac G4
in 1999. At the time of the G4 was launched, Motorola
Motorola
categorized all their PowerPC
PowerPC
models (former, current and future) according to what generation they adhered to, even renaming the older 603e core "G2". Motorola
Motorola
had a G5 project that never came to fruition, but the name stuck and Apple reused it when the 970 family launched in 2003 even if those were designed and built by IBM.

PowerPC
PowerPC
generations according to Motorola, ca 2000.[8] G1 - The 601, 500 and 800 family processors G2 - The 602, 603, 604, 620, 8200 and 5000 families G3 - The 750 and 8300 families G4 - The 7400 and 8400* families G5 - The 7500* and 8500 families ( Motorola
Motorola
didn't use the G5 moniker after Apple usurped the name) G6 - The 7600* (*) These designs didn't become real products.

Design features[edit]

Power Architecture

Made by Freescale

PowerPC
PowerPC
e series (2006)

e200 e300 e500 e600 e5500 e6500

Qor series (2008)

QorIQ Qorivva

Made by IBM

POWER ISA (1990) POWER series (1990)

POWER1 POWER2 POWER3 POWER4 POWER5 POWER6 POWER7 POWER8 POWER9

PowerPC
PowerPC
series (1992)

6xx 4xx 7xx 74xx 970

A2 RS64 (1996) RAD series (1997)

RAD6000 RAD750 RAD5500

IBM- Nintendo
Nintendo
collaboration

Gekko Broadway Espresso

Other

Titan PWRficient Cell Xenon

Related links

OpenPOWER Foundation AIM alliance RISC Blue Gene Power.org PAPR PReP CHRP AltiVec more...

Cancelled in gray, historic in italic

v t e

The PowerPC
PowerPC
is designed along RISC
RISC
principles, and allows for a superscalar implementation. Versions of the design exist in both 32-bit
32-bit
and 64-bit implementations. Starting with the basic POWER specification, the PowerPC
PowerPC
added:

Support for operation in both big-endian and little-endian modes; the PowerPC
PowerPC
can switch from one mode to the other at run-time (see below). This feature is not supported in the PowerPC
PowerPC
970. Single-precision forms of some floating point instructions, in addition to double-precision forms Additional floating point instructions at the behest of Apple A complete 64-bit specification that is backward compatible with the 32-bit
32-bit
mode A fused multiply–add A paged memory management architecture that is used extensively in server and PC systems. Addition of a new memory management architecture called Book-E, replacing the conventional paged memory management architecture for embedded applications. Book-E is application software compatible with existing PowerPC
PowerPC
implementations, but needs minor changes to the operating system.

Some instructions present in the POWER instruction set were deemed too complex and were removed in the PowerPC
PowerPC
architecture. Some removed instructions could be emulated by the operating system if necessary. The removed instructions are:

Conditional moves Load and store instructions for the quad-precision floating-point data type String instructions.

Endian modes[edit] Most PowerPC
PowerPC
chips switch endianness via a bit in the MSR (machine state register), with a second bit provided to allow the OS to run with a different endianness. Accesses to the "inverted page table" (a hash table that functions as a TLB with off-chip storage) are always done in big-endian mode. The processor starts in big-endian mode. In little-endian mode, the three lowest-order bits of the effective address are exclusive-ORed with a three bit value selected by the length of the operand. This is enough to appear fully little-endian to normal software. An operating system will see a warped view of the world when it accesses external chips such as video and network hardware. Fixing this warped view requires that the motherboard perform an unconditional 64-bit byte swap on all data entering or leaving the processor. Endianness
Endianness
thus becomes a property of the motherboard. An OS that operates in little-endian mode on a big-endian motherboard must both swap bytes and undo the exclusive-OR when accessing little-endian chips. AltiVec operations, despite being 128-bit, are treated as if they were 64-bit. This allows for compatibility with little-endian motherboards that were designed prior to AltiVec. An interesting side effect of this implementation is that a program can store a 64-bit value (the longest operand format) to memory while in one endian mode, switch modes, and read back the same 64-bit value without seeing a change of byte order. This will not be the case if the motherboard is switched at the same time. Mercury Systems
Mercury Systems
and Matrox
Matrox
ran the PowerPC
PowerPC
in little-endian mode. This was done so that PowerPC
PowerPC
devices serving as co-processors on PCI boards could share data structures with host computers based on x86. Both PCI and x86 are little-endian. OS/2
OS/2
and Windows NT
Windows NT
for PowerPC ran the processor in little-endian mode while Solaris, AIX
AIX
and Linux ran in big endian.[9] Some of IBM's embedded PowerPC
PowerPC
chips use a per-page endianness bit. None of the previous applies to them. Implementations[edit]

IBM
IBM
PowerPC
PowerPC
604e 200 MHz

Custom PowerPC
PowerPC
CPU from the Nintendo
Nintendo
Wii
Wii
video game console

The Freescale XPC855T Service Processor of a Sun SunFire
SunFire
V20z

The first implementation of the architecture was the PowerPC
PowerPC
601, released in 1992, based on the RSC, implementing a hybrid of the POWER1
POWER1
and PowerPC
PowerPC
instructions. This allowed the chip to be used by IBM
IBM
in their existing POWER1-based platforms, although it also meant some slight pain when switching to the 2nd generation "pure" PowerPC designs. Apple continued work on a new line of Macintosh computers based on the chip, and eventually released them as the 601-based Power Macintosh on March 14, 1994. IBM
IBM
also had a full line of PowerPC
PowerPC
based desktops built and ready to ship; unfortunately, the operating system that IBM
IBM
had intended to run on these desktops— Microsoft
Microsoft
Windows NT—was not complete by early 1993, when the machines were ready for marketing. Accordingly, and further because IBM
IBM
had developed animosity toward Microsoft, IBM decided to port OS/2
OS/2
to the PowerPC
PowerPC
in the form of Workplace OS. This new software platform spent three years (1992 to 1995) in development and was canceled with the December 1995 developer release, because of the disappointing launch of the PowerPC
PowerPC
620. For this reason, the IBM PowerPC
PowerPC
desktops did not ship, although the reference design (codenamed Sandalbow) based on the PowerPC 601
PowerPC 601
CPU was released as an RS/6000
RS/6000
model (Byte's April 1994 issue included an extensive article about the Apple and IBM
IBM
PowerPC
PowerPC
desktops). Apple, which also lacked a PowerPC
PowerPC
based OS, took a different route. Utilizing the portability platform yielded by the secret Star Trek project, the company ported the essential pieces of their Mac OS operating system to the PowerPC
PowerPC
architecture, and further wrote a 68k emulator that could run 68k
68k
based applications and the parts of the OS that had not been rewritten. The second generation was "pure" and includes the "low end" PowerPC 603 and "high end" PowerPC
PowerPC
604. The 603 is notable due to its very low cost and power consumption. This was a deliberate design goal on Motorola's part, who used the 603 project to build the basic core for all future generations of PPC chips. Apple tried to use the 603 in a new laptop design but was unable due to the small 8 KiB level 1 cache. The 68000 emulator in the Mac OS could not fit in 8 KiB and thus slowed the computer drastically.[citation needed] The 603e solved this problem by having a 16 KiB L1 cache, which allowed the emulator to run efficiently. In 1993, developers at IBM's Essex Junction, Burlington, Vermont facility started to work on a version of the PowerPC
PowerPC
that would support the Intel
Intel
x86 instruction set directly on the CPU. While this was just one of several concurrent power architecture projects that IBM
IBM
was working on, this chip began to be known inside IBM
IBM
and by the media as the PowerPC
PowerPC
615. Profitability concerns and rumors of performance issues in the switching between the x86 and native PowerPC instruction sets resulted in the project being canceled in 1995 after only a limited number of chips were produced for in-house testing. Aside the rumors, the switching process took only 5 cycles, or the amount of time needed for the processor to empty its instruction pipeline. Microsoft
Microsoft
also aided the processor's demise by refusing to support the PowerPC
PowerPC
mode.[10] The first 64-bit implementation is the PowerPC
PowerPC
620, but it appears to have seen little use because Apple didn't want to buy it and because, with its large die area, it was too costly for the embedded market. It was later and slower than promised, and IBM
IBM
used their own POWER3 design instead, offering no 64-bit "small" version until the late-2002 introduction of the PowerPC
PowerPC
970. The 970 is a 64-bit processor derived from the POWER4
POWER4
server processor. To create it, the POWER4
POWER4
core was modified to be backward-compatible with 32-bit
32-bit
PowerPC
PowerPC
processors, and a vector unit (similar to the AltiVec extensions in Motorola's 74xx series) was added. IBM's RS64 processors are a family of chips implementing the "Amazon" variant of the PowerPC
PowerPC
architecture. These processors are used in the RS/6000
RS/6000
and AS/400 computer families; the Amazon architecture includes proprietary extensions used by AS/400.[11] The POWER4
POWER4
and later POWER processors implement the Amazon architecture and replaced the RS64 chips in the RS/6000
RS/6000
and AS/400 families. IBM
IBM
developed a separate product line called the "4xx" line focused on the embedded market. These designs included the 401, 403, 405, 440, and 460. In 2004, IBM
IBM
sold their 4xx product line to Applied Micro Circuits Corporation (AMCC). AMCC continues to develop new high performance products, partly based on IBM's technology, along with technology that was developed within AMCC. These products focus on a variety of applications including networking, wireless, storage, printing/imaging and industrial automation. Numerically, the PowerPC
PowerPC
is mostly found in controllers in cars. For the automotive market, Freescale Semiconductor
Freescale Semiconductor
initially offered many variations called the MPC5xx
MPC5xx
family such as the MPC555, built on a variation of the 601 core called the 8xx and designed in Israel by MSIL ( Motorola
Motorola
Silicon Israel Limited). The 601 core is single issue, meaning it can only issue one instruction in a clock cycle. To this they add various bits of custom hardware, to allow for I/O on the one chip. In 2004, the next-generation four-digit 55xx devices were launched for the automotive market. These use the newer e200 series of PowerPC
PowerPC
cores. Networking is another area where embedded PowerPC
PowerPC
processors are found in large numbers. MSIL took the QUICC engine from the MC68302 and made the PowerQUICC
PowerQUICC
MPC860. This was a very famous processor used in many Cisco edge routers in the late 1990s. Variants of the PowerQUICC include the MPC850, and the MPC823/MPC823e. All variants include a separate RISC
RISC
microengine called the CPM that offloads communications processing tasks from the central processor and has functions for DMA. The follow-on chip from this family, the MPC8260, has a 603e-based core and a different CPM. Honda also uses PowerPC
PowerPC
processors for ASIMO.[12] In 2003, BAE SYSTEMS Platform Solutions delivered the Vehicle-Management Computer for the F-35 fighter jet. This platform consists of dual PowerPCs made by Freescale in a triple redundant setup.[13] Operating systems[edit] Operating systems that work on the PowerPC
PowerPC
architecture are generally divided into those that are oriented toward the general-purpose PowerPC
PowerPC
systems, and those oriented toward the embedded PowerPC systems. Operating systems with native support[edit]

AmigaOS 4 Apple classic Mac OS starting with System 7.1.2; and Copland, the original and canceled attempt at Mac OS 8 BeOS
BeOS
R5 Pro (BeBox, Macintosh and clones)

Haiku, experimental[14]

IBM
IBM
i; formerly named i5/OS, originally OS/400 MorphOS Plan 9 Inferno; from Bell Labs and maintained by Vita Nuova Holdings POSIX: Unix, Unix-like

Apple Mac OS X
Mac OS X
through Mac OS X
Mac OS X
Leopard 10.5.8 AIX Workplace OS, including a port of OS/2 FreeBSD, 32-bit
32-bit
and 64-bit ports[15] NetBSD, port designations for PowerPC
PowerPC
systems

ofppc released[16] macppc released[17] evbppc released[18] prep released[19] mvmeppc released[20] bebox experimental[21] amigappc very experimental[22]

OpenBSD, 32-bit
32-bit
macppc released port[23] Linux

CRUX PPC, with 32/ 64-bit releases[24] supported through release 2.0.1.1. Support was dropped from subsequent releases. Debian:

32-bit
32-bit
powerpc a released port since potato[25] Support has been removed from Debian
Debian
9 Stretch[26] 64-bit big-endian ppc64[27] in mostly stalled development 64-bit little-endian ppc64le a released port since jessie

Fedora with 32/ 64-bit ppc releases[28] up to version 12. PowerPC
PowerPC
is a Fedora secondary architecture from Fedora 16 onwards. Gentoo Linux, with 32-bit
32-bit
ppc releases and 64-bit ppc64 releases[29] MintPPC, support for Old World and New World 32/ 64-bit Macs based on Linux
Linux
Mint LXDE and Debian[30] MkLinux, Mach-kernel based distribution for older Macs, officially launched by Apple OpenSUSE, Full support for Old World and New World PowerMacs (32/64-bit), PS3 Cell, IBM
IBM
POWER systems through the release of 11.1. Support was dropped from subsequent releases. Red Hat Enterprise Linux, 32-bit
32-bit
ppc support was dropped following release of 5.11. Maintaining full support for 64-bit ppc64 in subsequent releases[31] SUSE Linux
Linux
Enterprise Server Ubuntu, community supported for versions released after 6.10[32] Yellow Dog Linux, full support for 32/64-bit; PS3

Solaris 2.5.1 PowerPC
PowerPC
edition on the PReP
PReP
platform

OpenSolaris, experimental[33][34]

Windows NT 3.51
Windows NT 3.51
and 4.0 ReactOS, PowerPC
PowerPC
port no longer under active development[35] CellOS for PlayStation 3

Embedded[edit]

VxWorks VxWorks
VxWorks
653 Nucleus RTOS LiveDevices RTA-OSEKLive Microware OS-9 MontaVista Linux Wind River Linux QNX Cisco IOS LynxOS PikeOS
PikeOS
RTOS and virtualization platform from SYSGO ELinOS
ELinOS
embedded Linux eCos RTEMS BlueCat embedded Linux
Linux
from LynuxWorks Operating System Embedded (OSE) from ENEA AB Integrity Juniper Networks
Juniper Networks
Junos
Junos
router and switch OS FreeRTOS Deos[36] SCIOPTA[37] RTOS, certified according IEC61508, EN50128 and ISO26262 Embedded PowerPC
PowerPC
Operating System by IBM[38]

Licensees[edit] Companies that have licensed the 64-bit POWER or 32-bit
32-bit
PowerPC
PowerPC
from IBM
IBM
include: 32-bit
32-bit
PowerPC[edit]

Altera, field-programmable gate array (FPGA) manufacturer now Intel Apple ('A' in original AIM alliance), has switched to Intel
Intel
in early 2006 Applied Micro Circuits Corporation
Applied Micro Circuits Corporation
(AMCC) Avago Technologies BAE Systems
BAE Systems
for RAD750
RAD750
processor, used in spacecraft and planetary landers Cisco Systems
Cisco Systems
for routers Culturecom for V-Dragon CPU Exponential Technology Kumyoung used in karaoke player CPU (Muzen and Vivaus series) LSI Logic Motorola
Motorola
(was Freescale Semiconductor
Freescale Semiconductor
now NXP
NXP
soon Qualcomm), as part of the original AIM alliance Rapport for Kilocore 1025 core CPU Samsung STMicroelectronics
STMicroelectronics
for the SPC5xx series Xilinx, FPGA
FPGA
maker, embedded PowerPC
PowerPC
in the Virtex-II Pro, Virtex-4, and Virtex-5 FPGAs

64-bit PowerPC[edit]

P.A. Semi Microsoft Hindustan Computers Ltd. Sony Freescale Semiconductor Toshiba

Game consoles[edit] Main article: PowerPC
PowerPC
based game consoles PowerPC
PowerPC
processors have been used in a number of video game consoles:

Bandai
Bandai
for its Bandai
Bandai
Pippin, designed by Apple Computer
Apple Computer
(1995) Microsoft, for the Xbox 360
Xbox 360
processor, Xenon[39] Nintendo
Nintendo
for the GameCube,[39] Wii, and Wii
Wii
U processors Sony
Sony
and Toshiba, for the Cell processor (inside the PlayStation 3
PlayStation 3
and other devices)[39]

Desktop computers[edit] The Power architecture is currently used in the following desktop computers:

Sam440ep, Sam440epFlex, based on an AMCC 440ep SoC, built by ACube Systems Sam460ex, based on an AMCC 460ex SoC, built by ACube Systems Nemo motherboard based around PA6T-1682M found in the AmigaOne
AmigaOne
X1000 from A-EON Technology Cyrus motherboard based around Freescale Qoriq P5020 found in the AmigaOne
AmigaOne
X5000 from A-EON Technology Tabor motherboard based around Freescale QorIQ
QorIQ
P1022 found in the forthcoming AmigaOne
AmigaOne
A1222 from A-EON Technology

Embedded applications[edit] The Power architecture is currently used in the following embedded applications:

National Instruments
National Instruments
Smart Cameras for machine vision Mars rover Curiosity

See also[edit]

Common Hardware Reference Platform (CHRP) List of PowerPC
PowerPC
processors Power Architecture Power Architecture
Power Architecture
Platform Reference (PAPR) PowerOpen Environment PowerPC Reference Platform (PReP) RTEMS
RTEMS
real-time operating system Vasm, a free assembler

References[edit]

^ a b c d Carlton, Jim (1999) [1997]. Apple: The Inside Story of Intrigue, Egomania and Business Blunders. ISBN 0099270730. OCLC 925000937.  ^ "Tech Files Columns, 1987-1990". Archived from the original on June 6, 2013.  ^ PowerPC
PowerPC
User Instruction Set Architecture Book I, version 2.02 Archived January 31, 2012, at the Wayback Machine. ^ a b "Forces Gather for PowerPC
PowerPC
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PowerPC
superscalar low-power microprocessor ^ G4 Is First PowerPC
PowerPC
With AltiVec - Due Mid-1999, Motorola’s Next Chip Aims at Macintosh, Networking Archived April 23, 2016, at the Wayback Machine. ^ PowerPC G4
PowerPC G4
Architecture White Paper Archived April 18, 2016, at the Wayback Machine. ^ Fact Sheet - Motorola
Motorola
PowerPC
PowerPC
Processor Archived April 19, 2016, at the Wayback Machine. ^ OS/2
OS/2
for PowerPC
PowerPC
Tidbits Archived January 31, 2016, at the Wayback Machine. ^ " Microsoft
Microsoft
killed the PowerPC
PowerPC
615". The Register. October 1, 1998. Archived from the original on February 7, 2009. Retrieved August 16, 2009.  ^ Adam T. Stallman; Frank G. Soltis (July 1, 1995). "Inside the PowerPC
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Further reading[edit]

May, Cathy; et al. (1994). The PowerPC
PowerPC
Architecture: A Specification for A New Family of RISC
RISC
Processors (2nd ed.). Morgan Kaufmann Publishers. ISBN 1-55860-316-6.  Hoxey, Steve (editor) et al. The PowerPC
PowerPC
Compiler Writer's Guide. Warthman Associates. ISBN 0-9649654-0-2. Motorola. Programming Environments Manual for 32-bit
32-bit
Implementations of the PowerPC
PowerPC
Architecture, a 640-page PDF manual. P/N MPCFPE32B/AD. IBM
IBM
(2000). Book E: Enhanced PowerPC
PowerPC
Architecture (3rd ed.) Duntemann, Jeff; Pronk, Ron (1994). Inside the PowerPC
PowerPC
Revolution. Coriolis Group Books. ISBN 1-883577-04-7.  PowerPC
PowerPC
Architecture, an IBM
IBM
article giving POWER and PowerPC
PowerPC
history

External links[edit]

PPC Overview - an overview of PowerPC
PowerPC
processors OS/2
OS/2
Warp, PowerPC
PowerPC
Edition review by Michal Necasek PowerPC
PowerPC
Architecture History Diagram

v t e

Motorola-Freescale- NXP
NXP
processors and microcontrollers

Processors

Industrial control unit

14500

6800 family

6800 6809

see also: Hitachi 6309

68HC11 68HC08 68HC05

68000 family

68000 68008 68010 68012 68020 68030 68040 68060 ColdFire DragonBall

Embedded system
Embedded system
68k-variants

68EC000 68EC020 68EC030 68EC040 68LC040 68EC060 68LC060

88000

MC88100

MC88110

Floating-point
Floating-point
coprocessors

68881 68882

Memory management unit

68451 68851

PowerPC
PowerPC
family

PPC e200 PPC 6xx/e300 PPC 7xx PPC e500 PPC 74xx/e600 PPC e5500 PowerQUICC QorIQ PPC e6500

ARM

i.MX

Microcontrollers

6801/6803 6802 6804 68HC05 68HC08 68HC11 68HC12 68HC16 683xx M·CORE MPC5xx PowerQUICC DSP568xx

DSPcontroller

PowerPC
PowerPC
5000 i.MX

v t e

Reduced instruction set computer
Reduced instruction set computer
(RISC) architectures

Berkeley RISC IBM
IBM
801 Stanford MIPS

Active

Altera
Altera
Nios II Analog Devices Blackfin ARC ARM Atmel AVR DLX eSi-RISC LatticeMico8 LatticeMico32 Meta MIPS OpenRISC Power

POWER PowerPC Cell

Renesas M32R Renesas SuperH Renesas V850 RISC-V S+core Sunway SPARC Unicore Xilinx MicroBlaze Xilinx PicoBlaze XMOS XCore XS1 VISC Mill

Historic

Alpha AMD Am29000 Apollo PRISM Atmel AVR32 Clipper CRISP DEC Prism Intel
Intel
i860 Intel
Intel
i960 MIPS-X Motorola
Motorola
88000 PA-RISC ROMP

v t e

Microcontrollers

Main

Single-board microcontroller Special
Special
function register

Architectures

68000 8051 ARM AVR PIC RISC-V

Families

4-bit

Am2900 MARC4 S1C6x TLCS-47 TMS1000 μCOM-4

8-bit

6800

68HC05 68HC08 68HC11 S08 RS08

6502

65C02 MELPS 740

78K 8048 8051

XC800

AVR COP8 H8 PIC10/12/16/17/18 ST6/ST7

STM8

Z8 Z80

eZ80 Rabbit 2000 TLCS-870

16-bit

68HC12/16 C166 CR16/C H8S MSP430 PIC24/dsPIC R8C RL78 TLCS-900 Z8000

32-bit

Am29000 ARM/Cortex-M

LPC

AVR32 CRX FR

FR-V

H8SX M32R 68000

ColdFire

PIC32 PowerPC

MPC5xx

Propeller STM32 TLCS-900 TriCore V850 RX Z80000

64-bit

PowerPC64

Interfaces

Programming

In-circuit serial programming
In-circuit serial programming
(ICSP) In-system programming
In-system programming
(ISP) Program and Debug Interface (PDI) High-voltage serial programming (HVSP) High voltage parallel programming (HVPP) Bootloader ROM aWire

Debugging

Nexus (standard) Joint Test Action Group
Joint Test Action Group
(JTAG)

debugWIRE (Atmel)

In-circuit debugging (ICD) In-circuit emulator (ICE) In-target probe (ITP)

Simulators

gpsim

Lists

List of common microcontrollers By manufacturer

Intel NXP/Freescale Renesas Electronics

List of Wi-Fi microcontrollers

See also

Embedded system Programmable logic controller

v t e

CPU technologies

Architecture

Turing machine Post–Turing machine Universal Turing machine Quantum Turing machine Belt machine Stack machine Register machine Counter machine Pointer machine Random access machine Random access stored program machine Finite-state machine Queue automaton Von Neumann Harvard (modified) Dataflow TTA Cellular Artificial neural network

Machine learning Deep learning Neural processing unit (NPU)

Convolutional neural network Load/store architecture Register memory architecture Endianness FIFO Zero-copy NUMA HUMA HSA Mobile computing Surface computing Wearable computing Heterogeneous computing Parallel computing Concurrent computing Distributed computing Cloud computing Amorphous computing Ubiquitous computing Fabric computing Cognitive computing Unconventional computing Hypercomputation Quantum computing Adiabatic quantum computing Linear optical quantum computing Reversible computing Reverse computation Reconfigurable computing Optical computing Ternary computer Analogous computing Mechanical computing Hybrid computing Digital computing DNA computing Peptide computing Chemical computing Organic computing Wetware computing Neuromorphic computing Symmetric multiprocessing
Symmetric multiprocessing
(SMP) Asymmetric multiprocessing
Asymmetric multiprocessing
(AMP) Cache hierarchy Memory hierarchy

ISA types

ASIP CISC RISC EDGE (TRIPS) VLIW (EPIC) MISC OISC NISC ZISC Comparison

ISAs

x86 z/Architecture ARM MIPS Power Architecture
Power Architecture
(PowerPC) SPARC Mill Itanium
Itanium
(IA-64) Alpha Prism SuperH V850 Clipper VAX Unicore PA-RISC MicroBlaze RISC-V

Word size

1-bit 2-bit 4-bit 8-bit 9-bit 10-bit 12-bit 15-bit 16-bit 18-bit 22-bit 24-bit 25-bit 26-bit 27-bit 31-bit 32-bit 33-bit 34-bit 36-bit 39-bit 40-bit 48-bit 50-bit 60-bit 64-bit 128-bit 256-bit 512-bit Variable

Execution

Instruction pipelining

Bubble Operand forwarding

Out-of-order execution

Register renaming

Speculative execution

Branch predictor Memory dependence prediction

Hazards

Parallel level

Bit

Bit-serial Word

Instruction Pipelining

Scalar Superscalar

Task

Thread Process

Data

Vector

Memory

Multithreading

Temporal Simultaneous (SMT) (Hyper-threading) Speculative (SpMT) Preemptive Cooperative Clustered Multi-Thread (CMT) Hardware scout

Flynn's taxonomy

SISD SIMD
SIMD
(SWAR) SIMT MISD MIMD

SPMD

Addressing mode

CPU performance

Instructions per second (IPS) Instructions per clock (IPC) Cycles per instruction (CPI) Floating-point
Floating-point
operations per second (FLOPS) Transactions per second (TPS) Synaptic Updates Per Second (SUPS) Performance per watt Orders of magnitude (computing) Cache performance measurement and metric

Core count

Single-core processor Multi-core processor Manycore processor

Types

Central processing unit
Central processing unit
(CPU) GPGPU AI accelerator Vision processing unit (VPU) Vector processor Barrel processor Stream processor Digital signal processor
Digital signal processor
(DSP) I/O processor/DMA controller Network processor Baseband processor Physics processing unit
Physics processing unit
(PPU) Coprocessor Secure cryptoprocessor ASIC FPGA FPOA CPLD Microcontroller Microprocessor Mobile processor Notebook processor Ultra-low-voltage processor Multi-core processor Manycore processor Tile processor Multi-chip module
Multi-chip module
(MCM) Chip stack multi-chip modules System on a chip
System on a chip
(SoC) Multiprocessor system-on-chip (MPSoC) Programmable System-on-Chip
System-on-Chip
(PSoC) Network on a chip (NoC)

Components

Execution unit (EU) Arithmetic logic unit
Arithmetic logic unit
(ALU) Address generation unit
Address generation unit
(AGU) Floating-point
Floating-point
unit (FPU) Load-store unit (LSU) Branch predictor Unified Reservation Station Barrel shifter Uncore Sum addressed decoder (SAD) Front-side bus Back-side bus Northbridge (computing) Southbridge (computing) Adder (electronics) Binary multiplier Binary decoder Address decoder Multiplexer Demultiplexer Registers Cache Memory management unit
Memory management unit
(MMU) Input–output memory management unit
Input–output memory management unit
(IOMMU) Integrated Memory Controller (IMC) Power Management Unit (PMU) Translation lookaside buffer
Translation lookaside buffer
(TLB) Stack engine Register file Processor register Hardware register Memory buffer register (MBR) Program counter Microcode
Microcode
ROM Datapath Control unit Instruction unit Re-order buffer Data buffer Write buffer Coprocessor Electronic switch Electronic circuit Integrated circuit Three-dimensional integrated circuit Boolean circuit Digital circuit Analog circuit Mixed-signal integrated circuit Power management integrated circuit Quantum circuit Logic gate

Combinational logic Sequential logic Emitter-coupled logic
Emitter-coupled logic
(ECL) Transistor–transistor logic
Transistor–transistor logic
(TTL) Glue logic

Quantum gate Gate array Counter (digital) Bus (computing) Semiconductor device Clock rate CPU multiplier Vision chip Memristor

Power management

APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating

Hardware security

Non-executable memory (NX bit) Memory Protection Extensions ( Intel
Intel
MPX) Intel
Intel
Secure Key Hardware restriction (firmware) Software Guard Extensions ( Intel
Intel
SGX) Trusted Execution Technology Trusted Platform Module
Trusted Platform Module
(TPM) Secure cryptoprocessor Hardware security module Hengzhi chip

Related

History of general-

.