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Tera MTA
The Cray MTA, formerly known as the Tera MTA, is a supercomputer architecture based on thousands of independent threads, fine-grain communication and synchronization between threads, and latency tolerance for irregular computations. Each MTA processor ( CPU) has a high-performance ALU with many independent register sets, each running an independent thread. For example, the Cray MTA-2 uses 128 register sets and thus 128 threads per CPU/ALU. All MTAs to date use a barrel processor arrangement, with a thread switch on every cycle, with blocked (stalled) threads skipped to avoid wasting ALU cycles. When a thread performs a memory read, execution blocks until data returns; meanwhile, other threads continue executing. With enough threads (concurrency), there are nearly always runnable threads to "cover" for blocked threads, and the ALUs stay busy. The memory system uses full/empty bits to ensure correct ordering. For example, an array is initially written with "empty" bits, and a ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Supercomputer
A supercomputer is a computer with a high level of performance as compared to a general-purpose computer. The performance of a supercomputer is commonly measured in floating-point operations per second ( FLOPS) instead of million instructions per second (MIPS). Since 2017, there have existed supercomputers which can perform over 1017 FLOPS (a hundred quadrillion FLOPS, 100 petaFLOPS or 100 PFLOPS). For comparison, a desktop computer has performance in the range of hundreds of gigaFLOPS (1011) to tens of teraFLOPS (1013). Since November 2017, all of the world's fastest 500 supercomputers run on Linux-based operating systems. Additional research is being conducted in the United States, the European Union, Taiwan, Japan, and China to build faster, more powerful and technologically superior exascale supercomputers. Supercomputers play an important role in the field of computational science, and are used for a wide range of computationally intensive tasks in var ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Arithmetic Logic Unit
In computing, an arithmetic logic unit (ALU) is a Combinational logic, combinational digital circuit that performs arithmetic and bitwise operations on integer binary numbers. This is in contrast to a floating-point unit (FPU), which operates on floating point numbers. It is a fundamental building block of many types of computing circuits, including the central processing unit (CPU) of computers, FPUs, and graphics processing units (GPUs). The inputs to an ALU are the data to be operated on, called operands, and a code indicating the operation to be performed; the ALU's output is the result of the performed operation. In many designs, the ALU also has status inputs or outputs, or both, which convey information about a previous operation or the current operation, respectively, between the ALU and external status registers. Signals An ALU has a variety of input and output net (electronics), nets, which are the electrical conductors used to convey Digital signal (electronics), digi ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
MTA-2
The Cray MTA-2 is a shared-memory MIMD computer marketed by Cray Inc. It is an unusual design based on the Tera computer designed by Tera Computer Company. The original Tera computer (also known as the ''MTA'') turned out to be nearly unmanufacturable due to its aggressive packaging and circuit technology. The MTA-2 was an attempt to correct these problems while maintaining essentially the same processor architecture respun in one silicon ASIC, down from some 26 gallium arsenide ASICs in the original MTA; and while regressing the network design from a 4-D torus topology to a less efficient but more scalable Cayley graph topology. The name ''Cray'' was added to the second version after Tera Computer Company bought the remains of the Cray Research division of Silicon Graphics in 2000 and renamed itself Cray Inc. The MTA-2 was not a commercial success, with only one moderately-sized 40-processor system ("Boomer") being sold to the United States Naval Research Laboratory in 2002, and ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Barrel Processor
A barrel processor is a CPU that switches between threads of execution on every cycle. This CPU design technique is also known as "interleaved" or "fine-grained" temporal multithreading. Unlike simultaneous multithreading in modern superscalar architectures, it generally does not allow execution of multiple instructions in one cycle. Like preemptive multitasking, each thread of execution is assigned its own program counter and other hardware registers (each thread's architectural state). A barrel processor can guarantee that each thread will execute one instruction every ''n'' cycles, unlike a preemptive multitasking machine, that typically runs one thread of execution for tens of millions of cycles, while all other threads wait their turn. A technique called C-slowing can automatically generate a corresponding barrel processor design from a single-tasking processor design. An ''n''-way barrel processor generated this way acts much like ''n'' separate multiprocessing cop ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Compiler
In computing, a compiler is a computer program that translates computer code written in one programming language (the ''source'' language) into another language (the ''target'' language). The name "compiler" is primarily used for programs that translate source code from a high-level programming language to a low-level programming language (e.g. assembly language, object code, or machine code) to create an executable program. Compilers: Principles, Techniques, and Tools by Alfred V. Aho, Ravi Sethi, Jeffrey D. Ullman - Second Edition, 2007 There are many different types of compilers which produce output in different useful forms. A ''cross-compiler'' produces code for a different CPU or operating system than the one on which the cross-compiler itself runs. A ''bootstrap compiler'' is often a temporary compiler, used for compiling a more permanent or better optimised compiler for a language. Related software include, a program that translates from a low-level language to a h ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Scalability
Scalability is the property of a system to handle a growing amount of work by adding resources to the system. In an economic context, a scalable business model implies that a company can increase sales given increased resources. For example, a package delivery system is scalable because more packages can be delivered by adding more delivery vehicles. However, if all packages had to first pass through a single warehouse for sorting, the system would not be as scalable, because one warehouse can handle only a limited number of packages. In computing, scalability is a characteristic of computers, networks, algorithms, networking protocols, programs and applications. An example is a search engine, which must support increasing numbers of users, and the number of topics it indexes. Webscale is a computer architectural approach that brings the capabilities of large-scale cloud computing companies into enterprise data centers. In mathematics, scalability mostly refers to closure u ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
GaAs
Gallium arsenide (GaAs) is a III-V direct band gap semiconductor with a zinc blende crystal structure. Gallium arsenide is used in the manufacture of devices such as microwave frequency integrated circuits, monolithic microwave integrated circuits, infrared light-emitting diodes, laser diodes, solar cells and optical windows. GaAs is often used as a substrate material for the epitaxial growth of other III-V semiconductors, including indium gallium arsenide, aluminum gallium arsenide and others. Preparation and chemistry In the compound, gallium has a +3 oxidation state. Gallium arsenide single crystals can be prepared by three industrial processes: * The vertical gradient freeze (VGF) process. * Crystal growth using a horizontal zone furnace in the Bridgman-Stockbarger technique, in which gallium and arsenic vapors react, and free molecules deposit on a seed crystal at the cooler end of the furnace. * Liquid encapsulated Czochralski (LEC) growth is used for producing high-puri ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
San Diego Supercomputer Center
The San Diego Supercomputer Center (SDSC) is an organized research unit of the University of California, San Diego (UCSD). SDSC is located at the UCSD campus' Eleanor Roosevelt College east end, immediately north the Hopkins Parking Structure. The current SDSC director is Michael L. Norman, UCSD physics professor, who succeeded noted grid computing pioneer Francine Berman. He was named director September 2010, having been interim director more than a year. SDSC was founded in 1985 and describes its mission as "developing and using technology to advance science." The SDSC was one of the five original NSF Supercomputing Centers and the National Science Foundation (NSF) continues to be a primary funder of the SDSC. Its research pursuits are high performance computing, grid computing, computational biology, geoinformatics, computational physics, computational chemistry, data management, scientific visualization, and computer networking. SDSC computational biosciences contribu ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
CMOS
Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss", ) is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. CMOS technology is used for constructing integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS), and other digital logic circuits. CMOS technology is also used for analog circuits such as image sensors (CMOS sensors), data converters, RF circuits (RF CMOS), and highly integrated transceivers for many types of communication. The CMOS process was originally conceived by Frank Wanlass at Fairchild Semiconductor and presented by Wanlass and Chih-Tang Sah at the International Solid-State Circuits Conference in 1963. Wanlass later filed US patent 3,356,858 for CMOS circuitry and it was granted in 1967. commercialized the technology with the trademark "COS-MO ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Naval Research Laboratory
The United States Naval Research Laboratory (NRL) is the corporate research laboratory for the United States Navy and the United States Marine Corps. It was founded in 1923 and conducts basic scientific research, applied research, technological development and prototyping. The laboratory's specialties include plasma physics, space physics, materials science, and tactical electronic warfare. NRL is one of the first US government scientific R&D laboratories, having opened in 1923 at the instigation of Thomas Edison, and is currently under the Office of Naval Research. As of 2016, NRL was a Navy Working Capital Fund activity, which means it is not a line-item in the US Federal Budget. Instead of direct funding from Congress, all costs, including overhead, were recovered through sponsor-funded research projects. NRL's research expenditures were approximately $1 billion per year. Research The Naval Research Laboratory conducts a wide variety of basic research and applied r ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
