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SPI-4.2
SPI-4.2 is a version of the System Packet Interface published by the Optical Internetworking Forum. It was designed to be used in systems that support OC-192 SONET interfaces and is sometimes used in 10 Gigabit Ethernet based systems. SPI-4 is an interface for packet and cell transfer between a physical layer (PHY) device and a link layer device, for aggregate bandwidths of OC-192 Asynchronous Transfer Mode and Packet over SONET/SDH (POS), as well as 10 Gigabit Ethernet applications. SPI-4 has two types of transfers—Data when the RCTL signal is deasserted; Control when the RCTL signal is asserted. The transmit and receive data paths include, respectively, (TDCLK, TDAT 5:0TCTL) and (RDCLK, RDAT 5:0 RCTL). The transmit and receive FIFO status channels include (TSCLK, TSTAT :0 and (RSCLK, RSTAT :0 respectively. A typical application of SPI-4.2 is to connect a framer device to a network processor. It has been widely adopted by the high speed networking marketplace. The inter ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
PL-4
{{about, PL-4, a networking protocol, the PRC missile PL-4, PL-4 (missile) PL-4 or POS-PHY Level 4 was the name of the interface that the interface SPI-4.2 is based on. It was proposed by PMC-Sierra to the Optical Internetworking Forum. The name means Packet Over SONET Physical layer level 4. PL-4 was developed by PMC-Sierra in conjunction with the Saturn Development Group. Context There are two broad categories of chip-to-chip interfaces. The first, exemplified by PCI-Express and HyperTransport, supports reads and writes of memory addresses. The second broad category carries user packets over 1 or more channels and is exemplified by the IEEE 802.3 family of Media Independent Interfaces and the Optical Internetworking Forum family of System Packet Interfaces. Of these last two, the family of System Packet Interfaces is optimized to carry user packets from many channels. The family of System Packet Interfaces is the most important packet-oriented, chip-to-chip interface family used b ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
System Packet Interface
The System Packet Interface (SPI) family of Interoperability Agreements from the Optical Internetworking Forum specify chip-to-chip, channelized, packet interfaces commonly used in synchronous optical networking and Ethernet applications. A typical application of such a packet level interface is between a framer (for optical network) or a MAC (for IP network) and a network processor. Another application of this interface might be between a packet processor ASIC and a traffic manager device. Context There are two broad categories of chip-to-chip interfaces. The first, exemplified by PCI-Express and HyperTransport, supports reads and writes of memory addresses. The second broad category carries user packets over 1 or more channels and is exemplified by the IEEE 802.3 family of Media Independent Interfaces and the Optical Internetworking Forum family of System Packet Interfaces. Of these last two, the family of System Packet Interfaces is optimized to carry user packets from man ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Optical Internetworking Forum
The Optical Internetworking Forum (OIF) is a prominent non-profit consortium that was founded in 1998. It promotes the development and deployment of interoperable computer networking products and services through implementation agreements (IAs) for optical networking products and component technologies including SerDes devices. OIF also creates benchmarks, performs worldwide interoperability testing, builds market awareness and promotes education for optical technologies. The Network Processing Forum merged into OIF in June 2006. The OIF has around a hundred member companies and has four face-to-face meetings per year. It is managed by Association Management Solutions and operates using parliamentary debate rules and transparent decision making. The technical content is member-driven. The OIF operates under a RAND licensing framework. It maintains liaison relationships with many other standards-developing organizations including the ITU, IEEE 802.3, the ONF, the InfiniBand ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SATURN Development Group
The SATURN Development Group was an important industry forum that enabled the specification of chip-to-chip interfaces for the communications industry. It was co-founded in 1992 by PMC-Sierra and Sun Microsystems. Several significant specifications were completed through its actions including PL-2, PL-3, and PL-4. Many important semiconductor devices were developed to these specifications. SATURN was also influential in the specification of the ATM Forum's physical layer "UTOPIA" standards. Initial members included SynOptics and Interphase. The first meeting was held in April 1992. By August 1993, the SATURN group had 28 members. After the formation of the Optical Internetworking Forum (OIF), two of the SATURN group's interfaces were successfully adopted by OIF. The PL-3 specification became SPI-3 and the PL-4 specification became SPI-4.2 SPI-4.2 is a version of the System Packet Interface published by the Optical Internetworking Forum. It was designed to be used in systems t ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Source-synchronous
Source-Synchronous clocking refers to a technique used for timing symbols on a digital interface. Specifically, it refers to the technique of having the transmitting device send a clock signal along with the data signals. The timing of the unidirectional data signals is referenced to the clock (often called the strobe) sourced by the same device that generates those signals, and not to a global clock (i.e. generated by a bus master). Compared to other digital clocking topologies like system-synchronous clocks, where a global clock source is fed to all devices in the system, a source-synchronous clock topology can attain far higher speeds. This type of clocking is common in high-speed interfaces between micro-chips, including DDR SDRAM, SGI XIO interface, Intel Front Side Bus A front-side bus (FSB) is a computer communication interface (bus) that was often used in Intel-chip-based computers during the 1990s and 2000s. The EV6 bus served the same function for competing AMD CPUs. ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Packet Over SONET/SDH
Packet over SONET/SDH, abbreviated POS, is a communications protocol for transmitting packets in the form of the Point to Point Protocol (PPP) over SDH or SONET, which are both standard protocols for communicating digital information using lasers or light emitting diodes (LEDs) over optical fibre at high line rates. POS is defined by RFC 2615 as PPP over SONET/SDH. PPP is the Point to Point Protocol that was designed as a standard method of communicating over point-to-point links. Since SONET/SDH uses point-to-point circuits, PPP is well suited for use over these links. Scrambling is performed during insertion of the PPP packets into the SONET/SDH frame to solve various security attacks including denial-of-service attacks and the imitation of SONET/SDH alarms. This modification was justified as cost-effective because the scrambling algorithm was already used by the standard used to transport ATM cells over SONET/SDH. However, scrambling can optionally be disabled to allow a node ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Asynchronous Transfer Mode
Asynchronous Transfer Mode (ATM) is a telecommunications standard defined by American National Standards Institute (ANSI) and ITU-T (formerly CCITT) for digital transmission of multiple types of traffic. ATM was developed to meet the needs of the Broadband Integrated Services Digital Network as defined in the late 1980s, and designed to integrate telecommunication networks. It can handle both traditional high-throughput data traffic and real-time, low-latency content such as telephony (voice) and video.ATM Forum, The User Network Interface (UNI), v. 3.1, , Prentice Hall PTR, 1995, page 2. ATM provides functionality that uses features of circuit switching and packet switching networks by using asynchronous time-division multiplexing.McDysan (1999), p. 287. In the OSI reference model data link layer (layer 2), the basic transfer units are called '' frames''. In ATM these frames are of a fixed length (53 octets) called ''cells''. This differs from approaches such as Internet Pro ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Physical Layer
In the seven-layer OSI model of computer networking, the physical layer or layer 1 is the first and lowest layer; The layer most closely associated with the physical connection between devices. This layer may be implemented by a PHY chip. The physical layer provides an electrical, mechanical, and procedural interface to the transmission medium. The shapes and properties of the electrical connectors, the frequencies to broadcast on, the line code to use and similar low-level parameters, are specified by the physical layer. Role The physical layer defines the means of transmitting a stream of raw bits over a physical data link connecting network nodes. The bitstream may be grouped into code words or symbols and converted to a physical signal that is transmitted over a transmission medium. The physical layer consists of the electronic circuit transmission technologies of a network. It is a fundamental layer underlying the higher level functions in a network, and can be imple ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Network Processor
A network processor is an integrated circuit which has a feature set specifically targeted at the networking application domain. Network processors are typically software programmable devices and would have generic characteristics similar to general purpose central processing units that are commonly used in many different types of equipment and products. History of development In modern telecommunications networks, information (voice, video, data) is transferred as packet data (termed packet switching) which is in contrast to older telecommunications networks that carried information as analog signals such as in the public switched telephone network (PSTN) or analog TV/Radio networks. The processing of these packets has resulted in the creation of integrated circuits (IC) that are optimised to deal with this form of packet data. Network processors have specific features or architectures that are provided to enhance and optimise packet processing within these networks. Network pr ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
LVDS
Low-voltage differential signaling (LVDS), also known as TIA/EIA-644, is a technical standard that specifies electrical characteristics of a differential, serial signaling standard. LVDS operates at low power and can run at very high speeds using inexpensive twisted-pair copper cables. LVDS is a physical layer specification only; many data communication standards and applications use it and add a data link layer as defined in the OSI model on top of it. LVDS was introduced in 1994, and has become popular in products such as LCD-TVs, in-car entertainment systems, industrial cameras and machine vision, notebook and tablet computers, and communications systems. The typical applications are high-speed video, graphics, video camera data transfers, and general purpose computer buses. Early on, the notebook computer and LCD display vendors commonly used the term LVDS instead of FPD-Link when referring to their protocol, and the term ''LVDS'' has mistakenly become synonymous with ' ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
FIFO (computing And Electronics)
Representation of a FIFO queue In computing and in systems theory, FIFO is an acronym for first in, first out (the first in is the first out), a method for organizing the manipulation of a data structure (often, specifically a data buffer) where the oldest (first) entry, or "head" of the queue, is processed first. Such processing is analogous to servicing people in a queue area on a first-come, first-served (FCFS) basis, i.e. in the same sequence in which they arrive at the queue's tail. FCFS is also the jargon term for the FIFO operating system scheduling algorithm, which gives every process central processing unit (CPU) time in the order in which it is demanded. FIFO's opposite is LIFO, last-in-first-out, where the youngest entry or "top of the stack" is processed first. A priority queue is neither FIFO or LIFO but may adopt similar behaviour temporarily or by default. Queueing theory encompasses these methods for processing data structures, as well as interactions between s ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
