Context
There are two broad categories of chip-to-chip interfaces. The first, exemplified byApplications
PL-4 was designed to be used in systems that supportTechnical details
The interface consists of (per direction): * sixteen LVDS pairs for the data path * one LVDS pair for control * one LVDS pair for clock at half of the data rate * two FIFO status lines running at 1/8 of the data rate * one status clock The clocking isTrivia
The name is anHistory
PL-4 is a descendant of PL-3 which itself is a descendant of theSee also
*External links