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SafeRTOS
FreeRTOS is a real-time operating system kernel for embedded devices that has been ported to 40 microcontroller platforms. It is distributed under the MIT License. History The FreeRTOS kernel was originally developed by Richard Barry around 2003, and was later developed and maintained by Barry's company, Real Time Engineers Ltd. In 2017, the firm passed stewardship of the FreeRTOS project to Amazon Web Services (AWS). Barry continues to work on FreeRTOS as part of an AWS team. With the transition to Amazon control, subsequent releases of the project also switched licensing from GPL version 2 (with special exceptions for static linking to proprietary code outside the FreeRTOS kernel itself) to MIT. Implementation FreeRTOS is designed to be small and simple. It is mostly written in the C programming language to make it easy to port and maintain. It also comprises a few assembly language functions where needed, mostly in architecture-specific scheduler routines. Process manageme ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Amazon Web Services
Amazon Web Services, Inc. (AWS) is a subsidiary of Amazon.com, Amazon that provides Software as a service, on-demand cloud computing computing platform, platforms and Application programming interface, APIs to individuals, companies, and governments, on a metered, pay-as-you-go basis. Clients will often use this in combination with elasticity (system resource), autoscaling (a process that allows a client to use more computing in times of high application usage, and then scale down to reduce costs when there is less traffic). These cloud computing web services provide various services related to networking, compute, storage, middleware, Internet of things, IoT and other processing capacity, as well as software tools via AWS server farms. This frees clients from managing, scaling, and patching hardware and operating systems. One of the foundational services is Amazon Elastic Compute Cloud (EC2), which allows users to have at their disposal a Virtualization, virtual Computer clus ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
PIC Microcontroller
PIC (usually pronounced as /pɪk/) is a family of microcontrollers made by Microchip Technology, derived from the PIC1640 originally developed by General Instrument's Microelectronics Division. The name PIC initially referred to ''Peripheral Interface Controller'',"MOS DATA 1976", General Instrument 1976 Databook and was subsequently expanded for a short time to include ''Programmable Intelligent Computer'', though the name PIC is no longer used as an acronym for any term. The first parts of the family were available in 1976; by 2013 the company had shipped more than twelve billion individual parts, used in a wide variety of embedded systems. The PIC was originally designed as a peripheral for the General Instrument CP1600, the first commercially available single-chip 16-bit microprocessor. To limit the number of pins required, the CP1600 had a complex highly- multiplexed bus which was difficult to interface with, so in addition to a variety of special-purpose peripherals ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Real-time Operating System
A real-time operating system (RTOS) is an operating system (OS) for real-time computing applications that processes data and events that have critically defined time constraints. A RTOS is distinct from a time-sharing operating system, such as Unix, which manages the sharing of system resources with a scheduler, data buffers, or fixed task prioritization in multitasking or multiprogramming environments. All operations must verifiably complete within given time and resource constraints or else fail safe. Real-time operating systems are event-driven and preemptive, meaning the OS can monitor the relevant priority of competing tasks, and make changes to the task priority. Characteristics A key characteristic of an RTOS is the level of its consistency concerning the amount of time it takes to accept and complete an application's task; the variability is "jitter". A "hard" real-time operating system (hard RTOS) has less jitter than a "soft" real-time operating system (soft RTOS); a l ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
MIT License
The MIT License is a permissive software license originating at the Massachusetts Institute of Technology (MIT) in the late 1980s. As a permissive license, it puts very few restrictions on reuse and therefore has high license compatibility. Unlike copyleft software licenses, the MIT License also permits reuse within proprietary software, provided that all copies of the software or its substantial portions include a copy of the terms of the MIT License and also a copyright notice. In 2015, the MIT License was the most popular software license on GitHub, and was still the most popular in 2025. Notable projects that use the MIT License include the X Window System, Ruby on Rails, Node.js, Lua (programming language), Lua, jQuery, .NET, Angular (web framework), Angular, and React (JavaScript library), React. License terms The MIT License has the identifier MIT in the SPDX License List. It is also known as the "#Ambiguity and variants, Expat License". It has the following terms: Co ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Microkernel
In computer science, a microkernel (often abbreviated as μ-kernel) is the near-minimum amount of software that can provide the mechanisms needed to implement an operating system (OS). These mechanisms include low-level address space management, thread (computing), thread management, and inter-process communication (IPC). If the hardware provides multiple Protection ring, rings or CPU modes, the microkernel may be the only software executing at the most privileged level, which is generally referred to as kernel mode, supervisor or kernel mode. Traditional operating system functions, such as device drivers, protocol stacks and file systems, are typically removed from the microkernel itself and are instead run in user space. In terms of the source code size, microkernels are often smaller than monolithic kernels. The MINIX 3 microkernel, for example, has only approximately 12,000 lines of code. History Microkernels trace their roots back to Danish computer pioneer Per Brinch ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SHAKTI (microprocessor)
Shakti (stylized as SHAKTI) is an open-source initiative by the Reconfigurable Intelligent Systems Engineering (RISE) group at IIT Madras to develop the first indigenous industrial-grade processor. The aims of the Shakti initiative include building an open source production-grade processor, complete systems on a chip, microprocessor development boards, and a Shakti-based software platform. The main focus of the team is computer architecture research to develop SoCs, which are competitive with commercial offerings in the market in area, power, and performance. The source code for Shakti is open-sourced under the Modified BSD License. V. Kamakoti carried out the SHAKTI Microprocessor Project, at Prathap Subrahmanyam Centre for Digital Intelligence and Secure Hardware Architecture (Department of Computer Science & Engineering, IIT Madras). The Ministry of Electronics and Information Technology supports it through its Digital India RISC-V initiative. Processors Shakti processors ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
RISC-V
RISC-V (pronounced "risk-five") is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. The project commenced in 2010 at the University of California, Berkeley. It transferred to the RISC-V Foundation in 2015, and from there to RISC-V International, a Swiss non-profit entity, in November 2019. Similar to several other RISC ISAs, e.g. Amber (processor), Amber (ARMv2)(2001), SuperH#J_Core, J-Core(2015), OpenRISC(2000), or OpenSPARC(2005), RISC-V is offered under royalty-free open-source licenses. The documents defining the RISC-V instruction set architecture (ISA) are offered under a Creative Commons license or a BSD licenses, BSD License. Mainline support for RISC-V was added to the Linux 5.17 kernel in 2022, along with its toolchain. In July 2023, RISC-V, in its 64-bit computing, 64-bit variant called riscv64, was included as an official architecture of Linux distribution Debian, in its Debian version histor ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ESP32
ESP32 is a family of low-cost, energy-efficient microcontrollers that integrate both Wi-Fi and Bluetooth capabilities. These chips feature a variety of processing options, including the Tensilica Xtensa LX6 microprocessor available in both dual-core and single-core variants, the Xtensa LX7 dual-core processor, or a single-core RISC-V microprocessor. In addition, the ESP32 incorporates components essential for wireless data communication such as built-in antenna switches, an RF balun, power amplifiers, low-noise receivers, filters, and power-management modules. Typically, the ESP32 is embedded on device-specific printed circuit boards or offered as part of development kits that include a variety of GPIO pins and connectors, with configurations varying by model and manufacturer. The ESP32 was designed by Espressif Systems and is manufactured by TSMC using their 40 nm process. It is a successor to the ESP8266 microcontroller. Features Features of the ESP32 include the foll ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Nios II
Nios II is a 32-bit embedded processor architecture designed specifically for the Altera family of field-programmable gate array (FPGA) integrated circuits. Nios II incorporates many enhancements over the original Nios architecture, making it more suitable for a wider range of embedded computing applications, from digital signal processing (DSP) to system-control. Nios II is a successor to Altera's first configurable 16-bit embedded processor Nios, introduced in 2000. Intel announced the discontinuation of Nios II in 2023, with its successor being Nios V, based on the RISC-V architecture. Key features Like the original Nios, the Nios II architecture is a RISC soft-core architecture which is implemented entirely in the programmable logic and memory blocks of Altera FPGAs. Unlike its predecessor it is a full 32-bit design: * 32 general-purpose 32-bit registers, * Full 32-bit instruction set, data path, and address space, * Single-instruction 32 × 32 multiply and divide ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
V850
V850 is a 32-bit RISC CPU architecture produced by Renesas Electronics for embedded microcontrollers. It was designed by NEC as a replacement for their earlier NEC V60 family, and was introduced shortly before NEC sold their designs to Renesas in the early 1990s. It has continued to be developed by Renesas . The V850 architecture is a load/store architecture with 32 32-bit general-purpose registers. It features a compressed instruction set with the most frequently used instructions mapped onto 16-bit half-words. Intended for use in ultra-low power consumption systems, such as those using 0.5 mW/ MIPS, the V850 has been widely used in a variety of applications, including optical disk drives, hard disk drives, mobile phones, car audio, and inverter compressors for air conditioners. Today, microarchitectures primarily focus on high performance and high reliability, such as the dual-lockstep redundant mechanism for the automotive industry; and the V850 and RH850 families ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Freescale ColdFire
The NXP ColdFire is a microprocessor that derives from the Motorola 68000 family architecture, manufactured for embedded systems development by NXP Semiconductors. It was formerly manufactured by Freescale Semiconductor (formerly the semiconductor division of Motorola) which merged with NXP in 2015. Instruction set The ColdFire instruction set is "assembly source" compatible (by means of translation software available from the vendor) and not entirely object code compatible with the 68000. When compared to classic 68k hardware, the instruction set differs mainly in that it no longer has support for the binary-coded decimal (BCD) packed data format; it removes a number of other, less used instructions; and most instructions that are kept support fewer addressing modes. Also, floating point intermediates are 64 bits and not 80 bits as in the 68881 and 68882 coprocessors. The instructions are only 16, 32, or 48 bits long, a simplification compared to the 68000 series. Models In Fe ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Intel 8051
The Intel MCS-51 (commonly termed 8051) is a single-chip microcontroller (MCU) series developed by Intel in 1980 for use in embedded systems. The architect of the Intel MCS-51 instruction set was John H. Wharton.. Intel's original versions were popular in the 1980s and early 1990s, and enhanced binary compatible derivatives remain popular today. It is a complex instruction set computer with separate memory spaces for program instructions and data. Intel's original MCS-51 family was developed using N-type metal–oxide–semiconductor ( NMOS) technology, like its predecessor Intel MCS-48, but later versions, identified by a letter C in their name (e.g., 80C51) use complementary metal–oxide–semiconductor ( CMOS) technology and consume less power than their NMOS predecessors. This made them more suitable for battery-powered devices. The family was continued in 1996 with the enhanced 8-bit MCS-151 and the 8/ 16/32-bit MCS-251 family of binary compatible microcontrollers. ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
