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Optical Internetworking Forum
The Optical Internetworking Forum (OIF) is a prominent non-profit consortium that was founded in 1998. It promotes the development and deployment of interoperable computer networking products and services through implementation agreements (IAs) for optical networking products and component technologies including SerDes devices. OIF also creates benchmarks, performs worldwide interoperability testing, builds market awareness and promotes education for optical technologies. The Network Processing Forum merged into OIF in June 2006. The OIF has around a hundred member companies and has four face-to-face meetings per year. It is managed by Association Management Solutions and operates using parliamentary debate rules and transparent decision making. The technical content is member-driven. The OIF operates under a RAND licensing framework. It maintains liaison relationships with many other standards-developing organizations including the ITU, IEEE 802.3, the ONF, the InfiniBand ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Non-profit
A nonprofit organization (NPO) or non-profit organisation, also known as a non-business entity, not-for-profit organization, or nonprofit institution, is a legal entity organized and operated for a collective, public or social benefit, in contrast with an entity that operates as a business aiming to generate a profit for its owners. A nonprofit is subject to the non-distribution constraint: any revenues that exceed expenses must be committed to the organization's purpose, not taken by private parties. An array of organizations are nonprofit, including some political organizations, schools, business associations, churches, social clubs, and consumer cooperatives. Nonprofit entities may seek approval from governments to be tax-exempt, and some may also qualify to receive tax-deductible contributions, but an entity may incorporate as a nonprofit entity without securing tax-exempt status. Key aspects of nonprofits are accountability, trustworthiness, honesty, and openness to eve ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Internet Engineering Task Force
The Internet Engineering Task Force (IETF) is a standards organization for the Internet and is responsible for the technical standards that make up the Internet protocol suite (TCP/IP). It has no formal membership roster or requirements and all its participants are volunteers. Their work is usually funded by employers or other sponsors. The IETF was initially supported by the federal government of the United States but since 1993 has operated under the auspices of the Internet Society, an international non-profit organization. Organization The IETF is organized into a large number of working groups and birds of a feather informal discussion groups, each dealing with a specific topic. The IETF operates in a bottom-up task creation mode, largely driven by these working groups. Each working group has an appointed chairperson (or sometimes several co-chairs); a charter that describes its focus; and what it is expected to produce, and when. It is open to all who want to particip ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SerDes Framer Interface
SerDes Framer Interface is a standard for telecommunications abbreviated as SFI. Variants include: * SFI-4 or SerDes Framer Interface Level 4, a standardized Electrical Interface by the Optical Internetworking Forum (OIF) for connecting a synchronous optical networking (SONET) framer component to an optical serializer/deserializer (SerDes) for Optical Carrier transmission rate OC-192 interfaces at about 10 Gigabits per second. * SFI-5 or SerDes Framer Interface Level 5, a standardized Electrical Interface by the OIF for connecting a SONET Framer component to an optical SerDes for OC-768, about 40 Gbit/s. Electrically, it consists of 16 pairs of SerDes channels each running at 3.125 Gbit/s which gives an aggregate bandwidth of 50 Gbit/s accommodating up to 25% of Forward Error Correction See also * XFP transceiver * System Packet Interface * Common Electrical I/O The Common Electrical I/O (CEI) refers to a series of influential Interoperability Agreements (IAs) that have bee ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Interlaken (networking)
Interlaken is a royalty-free interconnect protocol. It was invented by Cisco Systems and Cortina Systems in 2006, optimized for high-bandwidth and reliable packet transfers. It builds on the channelization and per channel flow control features of SPI-4.2, while reducing the number of integrated circuit (chip) I/O pins by using high speed SerDes technology. Bundles of serial links create a logical connection between components with multiple channels, backpressure capability, and data-integrity protection to boost the performance of communications equipment. Interlaken manages speeds of up to 6 Gbit/s per pin (lane) and large numbers of lanes can form an Interlaken interface. It was designed to handle high-speed (10 Gigabit Ethernet, 100 Gigabit Ethernet and beyond) computer network A computer network is a set of computers sharing resources located on or provided by network nodes. The computers use common communication protocols over digital interconnections to communicate ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SPI-3
SPI-3 or System Packet Interface Level 3 is the name of a chip-to-chip, channelized, packet interface widely used in high-speed communications devices. It was proposed by PMC-Sierra based on their PL-3 interface to the Optical Internetworking Forum and adopted in June 2000. PL-3 was developed by PMC-Sierra in conjunction with the SATURN Development Group. Applications It was designed to be used in systems that support OC-48 SONET interfaces . A typical application of SPI-3 is to connect a framer device to a network processor. It has been widely adopted by the high speed networking marketplace. Technical details The interface consists of (per direction): * 32 TTL signals for the data path * 8 TTL signals for control * one TTL signal for clock * 8 TTL signals for optional additional multi-channel status There are several clocking options. The interface operates around 100 MHz. Implementations of SPI-3 (PL-3) have been produced which allow somewhat higher clock rates. Thi ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
System Packet Interface
The System Packet Interface (SPI) family of Interoperability Agreements from the Optical Internetworking Forum specify chip-to-chip, channelized, packet interfaces commonly used in synchronous optical networking and Ethernet applications. A typical application of such a packet level interface is between a framer (for optical network) or a MAC (for IP network) and a network processor. Another application of this interface might be between a packet processor ASIC and a traffic manager device. Context There are two broad categories of chip-to-chip interfaces. The first, exemplified by PCI-Express and HyperTransport, supports reads and writes of memory addresses. The second broad category carries user packets over 1 or more channels and is exemplified by the IEEE 802.3 family of Media Independent Interfaces and the Optical Internetworking Forum family of System Packet Interfaces. Of these last two, the family of System Packet Interfaces is optimized to carry user packets from man ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
PMC-Sierra
PMC-Sierra was a global fabless semiconductor company with offices worldwide that developed and sold semiconductor devices into the storage, communications, optical networking, printing, and embedded computing marketplaces. On January 15, 2016, Microsemi Corporation completed acquisition of PMC-Sierra through Microsemi's subsidiary Lois Acquisition. History Sierra Semiconductor was founded in 1984 in San Jose, California by James Diller. It received funding on January 11, 1984 from Sequoia Capital, and went public in 1991. Pacific Microelectronics Centre (PMC) in Burnaby, British Columbia, Canada, was spun off from Microtel Pacific Research (the research arm of BC TEL at the time) to develop Asynchronous Transfer Mode (ATM) and later SONET integrated circuits (chips). With investment from Sierra Semiconductor, PMC was established in 1992 as a private company focused on providing networking semiconductors, and became a wholly owned, independently operated subsidiary of Sierr ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
PL-3
PL-3 or POS-PHY Level 3 is a network protocol. It is the name of the interface that the Optical Internetworking Forum's SPI-3 Interoperability Agreement is based on. It was proposed by PMC-Sierra to the Optical Internetworking Forum and adopted in June 2000. The name means Packet Over SONET Physical layer level 3. PL-3 was developed by PMC-Sierra in conjunction with the SATURN Development Group. The name is an acronym of an acronym of an acronym as the P in PL stands for "POS-PHY" and the S in POS-PHY stands for "SONET" (Synchronous Optical Network). The L in PL stands for "Layer". Context There are two broad categories of chip-to-chip interfaces. The first, exemplified by PCI-Express and HyperTransport, supports reads and writes of memory addresses. The second broad category carries user packets over 1 or more channels and is exemplified by the IEEE 802.3 family of Media Independent Interfaces and the Optical Internetworking Forum family of System Packet Interfaces. Of these ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
FPGA
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturinghence the term '' field-programmable''. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). Circuit diagrams were previously used to specify the configuration, but this is increasingly rare due to the advent of electronic design automation tools. FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects allowing blocks to be wired together. Logic blocks can be configured to perform complex combinational functions, or act as simple logic gates like AND and XOR. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. Many FPGAs can be reprogrammed to implement different logic functions, allowing flexible reconfigurabl ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ASIC
An application-specific integrated circuit (ASIC ) is an integrated circuit (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a digital voice recorder or a high-efficiency video codec. Application-specific standard product (ASSP) chips are intermediate between ASICs and industry standard integrated circuits like the 7400 series or the 4000 series. ASIC chips are typically fabricated using metal-oxide-semiconductor (MOS) technology, as MOS integrated circuit chips. As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 logic gates to over 100 million. Modern ASICs often include entire microprocessors, memory blocks including ROM, RAM, EEPROM, flash memory and other large building blocks. Such an ASIC is often termed a SoC (system-on-chip). Designers of digital ASICs often use a hardware description ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Common Electrical I/O
The Common Electrical I/O (CEI) refers to a series of influential Interoperability Agreements (IAs) that have been published by the Optical Internetworking Forum (OIF). CEI defines the electrical and jitter requirements for 3.125, 6, 11, 25-28, and 56 Gbit/s electrical interfaces. CEI, the Common Electrical I/O The Common Electrical I/O (CEI) Interoperability Agreement published by the OIF defines the electrical and jitter requirements for 3.125, 6, 11, 25-28, and 56 Gbit/s SerDes interfaces. This CEI specification has defined SerDes interfaces for the industry since 2004, and it has been highly influential. The development of electrical interfaces at the OIF began with SPI-3 in 2000, and the first differential interface was published in 2003. The seventh generation electrical interface, CEI-56G, defines five reaches of 56 Gbit/s interfaces. The OIF began work on its eighth generation with its CEI-112G project. CEI has influenced or has been adopted or adapted in many other seri ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
