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Nios Embedded Processor
Nios was Altera's first configurable 16-bit embedded processor for its FPGA product-line. For new designs, Altera recommends the 32-bit Nios II. See also * LatticeMico8 * LatticeMico32 * MicroBlaze * PicoBlaze * Micon P200 Micon the Younger of Athens, simply Micon or Mikon ( el, Μίκων) was an ancient Greek painter and sculptor from the middle of the 5th century BC. He was closely associated with Polygnotus of Thasos, in conjunction with whom he adorned the Stoa ... References Soft microprocessors {{Microcompu-stub ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Altera
Altera Corporation was a manufacturer of programmable logic devices (PLDs) headquartered in San Jose, California. It was founded in 1983 and acquired by Intel in 2015. The main product lines from Altera were the flagship Stratix series, mid-range Arria series, and lower-cost Cyclone series system on a chip field-programmable gate arrays (FPGAs); the MAX series complex programmable logic device and non-volatile FPGAs; Quartus design software; and Enpirion PowerSoC DC-DC power solutions. The company was founded in 1983 by semiconductor veterans Rodney Smith, Robert Hartmann, James Sansbury, and Paul Newhagen with $500,000 in seed money. The name of the company was a play on "alterable", the type of chips the company created. In 1984, the company formed a long-running design partnership with Intel, and 1988, became a public company via an initial public offering. In 1994, Altera acquired the PLD business of Intel for $50 million. On December 28, 2015, the company was acquired by ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
FPGA
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturinghence the term '' field-programmable''. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). Circuit diagrams were previously used to specify the configuration, but this is increasingly rare due to the advent of electronic design automation tools. FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects allowing blocks to be wired together. Logic blocks can be configured to perform complex combinational functions, or act as simple logic gates like AND and XOR. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. Many FPGAs can be reprogrammed to implement different logic functions, allowing flexible reconfigurabl ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Nios II
Nios II is a 32-bit embedded processor architecture designed specifically for the Altera family of field-programmable gate array (FPGA) integrated circuits. Nios II incorporates many enhancements over the original Nios architecture, making it more suitable for a wider range of embedded computing applications, from digital signal processing (DSP) to system-control. Nios II is a successor to Altera's first configurable 16-bit embedded processor Nios, introduced in 2000. Key features Like the original Nios, the Nios II architecture is a RISC soft-core architecture which is implemented entirely in the programmable logic and memory blocks of Altera FPGAs. Unlike its predecessor it is a full 32-bit design: * 32 general-purpose 32-bit registers, * Full 32-bit instruction set, data path, and address space, * Single-instruction 32 × 32 multiply and divide producing a 32-bit result. The soft-core nature of the Nios II processor lets the system designer specify and generate a custom Ni ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
LatticeMico8
The LatticeMico8 is an 8-bit microcontroller reduced instruction set computer (RISC) soft processor core optimized for field-programmable gate arrays (FPGAs) and crossover programmable logic device architecture from Lattice Semiconductor. Combining a full 18-bit wide instruction set with 32 general purpose registers, the LatticeMico8 is a flexible Verilog reference design suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial, and automotive. The core consumes minimal device resources, less than 200 lookup tables (LUTs) in the smallest configuration, while maintaining a broad feature set. The LatticeMico8 is licensed under a new free (IP) core license, the first such license offered by any FPGA supplier. The main benefits of using the IP core are greater flexibility, improved portability, and no cost. This new agreement provides some of the benefits of standard open-source license An open-source license is a type of license for ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
LatticeMico32
LatticeMico32 is a 32-bit microprocessor reduced instruction set computer (RISC) soft core from Lattice Semiconductor optimized for field-programmable gate arrays (FPGAs). It uses a Harvard architecture, which means the instruction and data buses are separate. Bus arbitration logic can be used to combine the two buses, if desired. LatticeMico32 is licensed under a free (IP) core license. This means that the Mico32 is not restricted to Lattice FPGAs, and can be legally used on any host architecture (FPGA, application-specific integrated circuit (ASIC), or software emulation, e.g., QEMU). It is possible to embed a LatticeMico32 core into Xilinx and Altera FPGAs, in addition to the Lattice Semiconductor parts the LatticeMico32 was developed for. AMD PowerTune uses LatticeMico32. The CPU core and the development toolchain are available as source-code, allowing third parties to implement changes to the processor architecture. Features * RISC load/store architecture * 32-bit data path ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
PicoBlaze
PicoBlaze is the designation of a series of three free soft processor cores from Xilinx for use in their FPGA and CPLD products. They are based on an 8-bit RISC architecture and can reach speeds up to 100 MIPS on the Virtex 4 FPGA's family. The processors have an 8-bit address and data port for access to a wide range of peripherals. The license of the cores allows their free use, albeit only on Xilinx devices, and they come with development tools. Third-party tools are available from Mediatronix and others. Also PacoBlaze, a behavioral and device independent implementation of the cores exists and is released under the BSD License. The PauloBlaze is an open source VHDL implementation under the Apache License. The PicoBlaze design was originally named KCPSM which stands for "Constant(K) Coded Programmable State Machine" (formerly "Ken Chapman's PSM"). Ken Chapman was the Xilinx systems designer who devised and implemented the microcontroller. Instantiation When instantiating a P ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Micon P200
Micon the Younger of Athens, simply Micon or Mikon ( el, Μίκων) was an ancient Greek painter and sculptor from the middle of the 5th century BC. He was closely associated with Polygnotus of Thasos, in conjunction with whom he adorned the Stoa poikile ("Painted Portico"), at Athens, with paintings of the Battle of Marathon and other battles. He also painted in the Anakeion at Athens. His daughter was the painter Timarete Timarete ( el, Τιμαρέτη) (or Thamyris, Tamaris, Thamar; 5th century BC), was an ancient Greek painter. She was the daughter of the painter Micon the Younger of Athens. According to Pliny the Elder, she "scorned the duties of women and p .... References * {{Authority control 5th-century BC Greek sculptors Ancient Greek sculptors Ancient Greek painters Ancient Athenian sculptors 5th-century BC painters ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
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