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List Of VIA Nano Microprocessors
The Nano microprocessor from VIA Technologies is an eighth-generation CPU targeted at the consumer and embedded market. Desktop and mobile processors Nano L "Nano 2000" series (65nm) * All models support: '' MMX, SSE, SSE2, SSE3, SSSE3, x86-64, NX bit, VT-x (stepping 3 and higher), VIA PadLock (SHA, AES, RNG)'', VIA PowerSaver "Nano 3000" series (65nm) * All models support: '' MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, x86-64, NX bit, VT-x, VIA PadLock (SHA, AES, RNG)'', VIA PowerSaver "Nano X2" (40nm) * All models support: '' MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, x86-64, NX bit, VT-x, VIA PadLock (SHA, AES, RNG)'', VIA PowerSaver * Two Nano 3000 (Isaiah) in the same die "Nano QuadCore" (40nm) * All models support: '' MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, x86-64, NX bit, VT-x, VIA PadLock (SHA, AES, RNG)'', VIA PowerSaver * Two Nano x2 (Isaiah) in a Multi-chip module Nano C "Nano QuadCore" (28nm) * All models support: '' MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
VIA Nano
The VIA Nano (formerly Code name#Commercial code names in the computer industry, code-named VIA Isaiah) is a 64-bit CPU for personal computers. The VIA Nano was released by VIA Technologies in 2008 after five years of development by its CPU division, Centaur Technology. This Isaiah 64-bit architecture was designed from scratch, unveiled on 24 January 2008, and launched on 29 May, including low-voltage variants and the Nano brand name. The processor supports a number of VIA-specific x86 extensions designed to boost efficiency in low-power appliances. History Unlike Intel and AMD, VIA uses two distinct development code names for each of its CPU cores. In this case, the codename 'CN' was used in the United States by Centaur Technology. Biblical names are used as codes by VIA in Taiwan, and Isaiah was the choice for this particular processor and architecture. It is expected that the VIA Isaiah will be twice as fast in integer performance and four times as fast in floating-point p ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
VIA PadLock
VIA PadLock is a central processing unit (CPU) instruction set extension to the x86 microprocessor instruction set architecture (ISA) found on processors produced by VIA Technologies and Zhaoxin. Introduced in 2003 with the VIA Centaur CPUs, the additional instructions provide hardware-accelerated random number generation (RNG), Advanced Encryption Standard (AES), SHA-1, SHA256, and Montgomery modular multiplication. Instructions The PadLock instruction set can be divided into four subsets: * Random number generation (RNG) ** XSTORE: Store Available Random Bytes (aka XSTORERNG) ** REP XSTORE: Store ECX Random Bytes * Advanced cryptography engine (ACE) - for AES crypto; two versions ** REP XCRYPTECB: Electronic code book ** REP XCRYPTCBC: Cipher Block Chaining ** REP XCRYPTCTR: Counter Mode (ACE2) ** REP XCRYPTCFB: Cipher Feedback Mode ** REP XCRYPTOFB: Output Feedback Mode * SHA hash engine (PHE) ** REP XSHA1: Hash Function SHA-1 ** REP XSHA256: Hash Function SHA-256 * Montgome ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
List Of VIA Microprocessors
This article lists x86-compliant microprocessors sold by VIA Technologies, grouped by technical merits: cores within same group have much in common. Cyrix design ( Cyrix III) * All models support: '' MMX, 3DNow!'' Centaur Technology design Cyrix III, C3 * All models support: '' MMX, 3DNow!'' C3, C7 * All models support: '' MMX, SSE'' * SSE2, SSE3, NX bit supported by Esther (C5J) * x86 (no x86-64) Nano * First VIA processor with x86-64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit extension of the x86 instruction set architecture, instruction set. It was announced in 1999 and first available in the AMD Opteron family in 2003. It introduces two new ope ... instruction set * See List of Nano microprocessors CHA * Announced 2019. Discontinued in 2021 with the sales of Centaur to Intel. * 8 cores + "NCORE" neural processor for AI acceleration. * supports: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AES AVX AVX2 FMA3 SHA AVX ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Zhaoxin
Zhaoxin (Shanghai Zhaoxin Semiconductor Co., Ltd.; , ) is a fabless semiconductor company, created in 2013 as a joint venture between VIA Technologies and the Shanghai Municipal Government. The company manufactures x86-compatible desktop and laptop CPUs. The term '' Zhào xīn'' means ''million core''.In China 兆 can mean either short-scale million (1e6) or trillion (1e12). However, for IT-related topics 兆 always means mega/million in mainland China. The processors are created mainly for the Chinese market: the venture is an attempt to reduce the Chinese dependence on foreign technology. Background ''Zhaoxin'' is a joint venture between VIA Technologies and the Shanghai Municipal Government. In 2021 it was reported that VIA has a 14.75% shareholding in the company. China has a domestic policy to "replace all foreign hardware and software from its public infrastructure with homegrown solutions" by 2023 (the so-called 3–5–2 policy). VIA holds an x86 license which allows ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
AVX2
Advanced Vector Extensions (AVX, also known as Gesher New Instructions and then Sandy Bridge New Instructions) are SIMD extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They were proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge microarchitecture shipping in Q1 2011 and later by AMD with the Bulldozer microarchitecture shipping in Q4 2011. AVX provides new features, new instructions, and a new coding scheme. AVX2 (also known as Haswell New Instructions) expands most integer commands to 256 bits and introduces new instructions. They were first supported by Intel with the Haswell microarchitecture, which shipped in 2013. AVX-512 expands AVX to 512-bit support using a new EVEX prefix encoding proposed by Intel in July 2013 and first supported by Intel with the Knights Landing co-processor, which shipped in 2016. In conventional processors, AVX-512 was introduced with Skylak ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Multi-chip Module
A multi-chip module (MCM) is generically an electronic assembly (such as a package with a number of conductor terminals or Lead (electronics), "pins") where multiple integrated circuits (ICs or "chips"), semiconductor Die (integrated circuit), dies and/or other discrete components are integrated, usually onto a unifying substrate, so that in use it can be treated as if it were a larger IC. Other terms for MCM packaging include "heterogeneous integration" or "hybrid integrated circuit". The advantage of using MCM packaging is it allows a manufacturer to use multiple components for modularity and/or to improve yields over a conventional monolithic IC approach. A Flip Chip Multi-Chip Module (FCMCM) is a multi-chip module that uses flip chip technology. A FCMCM may have one large die and several smaller dies all on the same module. Overview Multi-chip modules come in a variety of forms depending on the complexity and development philosophies of their designers. These can range from ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SSE4
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper;Intel Streaming SIMD Extensions 4 (SSE4) Instruction Set Innovation , Intel. more precise details of 47 instructions became available at the Spring 2007 Intel Developer Forum in , in the presentation. SSE4 extended the SSE3 instruction set which was released in early 2004. All software using previous Intel SIMD instructio ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
PowerSaver
VIA LongHaul is a CPU speed throttling and power saving technology developed by VIA Technologies. By executing specialized instructions, software can exercise fine control on the bus-to-core frequency ratio and CPU core voltage. When the system first boots, the ratio and voltage are set to hardware defaults. While the operating system runs, a ''CPU driver'' controls the throttling according to how much load is put on the CPU. This fine control over the CPU's operating parameters brings LongHaul in contrast to other competing technologies, where a CPU is typically allowed to switch between only two states - one that is fast but power-consuming and one that is slow but uses less power. However LongHaul is considered similar to Transmeta's LongRun technology. There are 3 versions of LongHaul: * Version 1 only supports dynamic frequency scaling and is implemented in the Cyrix III Samuel (C5A) core and C3 Samuel 2 (C5B) stepping 0 core. * Version 2 adds voltage scaling and is ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
X86 Virtualization
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-assisted virtualization capabilities while attaining reasonable performance. In 2005 and 2006, both Intel ( VT-x) and AMD ( AMD-V) introduced limited hardware virtualization support that allowed simpler virtualization software but offered very few speed benefits. Greater hardware support, which allowed substantial speed improvements, came with later processor models. Software-based virtualization The following discussion focuses only on virtualization of the x86 architecture protected mode. In protected mode the operating system kernel runs at a higher privilege such as ring 0, and applications at a lower privilege such as ring 3. In software-based virtualization, a host OS has direct access to hardware while the guest OSs have limit ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
VIA Technologies
VIA Technologies, Inc. () is a Taiwanese manufacturer of integrated circuits, mainly motherboard chipsets, CPUs, and memory. It was once the world's largest independent manufacturer of motherboard chipsets. As a fabless semiconductor company, VIA conducts research and development of its chipsets in-house, then subcontracts the actual (silicon) manufacturing to third-party merchant foundries such as TSMC. VIA is also the parent company of VIA Labs Inc. (VLI, ). As an independently traded subsidiary, VLI develops and markets USB 3, USB 4, USB Type-C, and USB PD controllers for computer peripherals and mobile devices. History The company was founded in 1987, in Fremont, California, USA by Cher Wang. In 1992, it was decided to move the headquarters to Taipei, Taiwan in order to establish closer partnerships with the substantial and growing IT manufacturing base in Taiwan and neighbouring China. In 1999, VIA acquired most of Cyrix, then a division of National Semiconductor. Th ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
NX Bit
The NX bit (no-execute bit) is a processor feature that separates areas of a virtual address space (the memory layout a program uses) into sections for storing data or program instructions. An operating system supporting the NX bit can mark certain areas of the virtual address space as non-executable, preventing the processor from running any code stored there. This technique, known as executable space protection or Write XOR Execute, protects computers from malicious software that attempts to insert harmful code into another program’s data storage area and execute it, such as in a buffer overflow attack. The term "NX bit" was introduced by Advanced Micro Devices (AMD) as a marketing term. Intel markets this feature as the XD bit (execute disable), while the MIPS architecture refers to it as the XI bit (execute inhibit). In the ARM architecture, introduced in ARMv6, it is known as XN (execute never). The term NX bit is often used broadly to describe similar executable space p ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
