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E (verification Language)
e is a hardware verification language (HVL) which is tailored to implementing highly flexible and reusable verification testbenches. History ''e'' was first developed in 1992 in Israel by Yoav Hollander for his Specman software. In 1995 he founded a company, ''InSpec'' (later renamed Verisity), to commercialize the software. The product was introduced at the 1996 Design Automation Conference.Samir Palnitkar: ''Design verification with e'', Prentice Hall PTR. October 5, 2003. Verisity has since been acquired by Cadence Design Systems. Features Main features of ''e'' are: * Random and constrained random stimulus generation * Functional coverage metric definition and collection * Temporal language that can be used for writing assertions * Aspect-oriented programming language with reflection capability * Language is DUT-neutral in that you can use a single ''e'' testbench to verify a SystemC/C++ model, an RTL model, a gate level model, or even a DUT residing in a hardware ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Aspect-oriented Programming
In computing, aspect-oriented programming (AOP) is a programming paradigm that aims to increase modularity by allowing the separation of cross-cutting concerns. It does so by adding behavior to existing code (an advice) ''without'' modifying the code itself, instead separately specifying which code is modified via a "pointcut" specification, such as "log all function calls when the function's name begins with 'set. This allows behaviors that are not central to the business logic (such as logging) to be added to a program without cluttering the code core to the functionality. AOP includes programming methods and tools that support the modularization of concerns at the level of the source code, while aspect-oriented software development refers to a whole engineering discipline. Aspect-oriented programming entails breaking down program logic into distinct parts (so-called ''concerns'', cohesive areas of functionality). Nearly all programming paradigms support some level of groupi ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Hardware Verification Language
A hardware verification language, or HVL, is a programming language used to verify the designs of electronic circuits written in a hardware description language. HVLs typically include features of a high-level programming language like C++ or Java as well as features for easy bit-level manipulation similar to those found in HDLs. Many HVLs will provide constrained random stimulus generation, and functional coverage constructs to assist with complex hardware verification. SystemVerilog, OpenVera, e, and SystemC are the most commonly used HVLs. SystemVerilog attempts to combine HDL and HVL constructs into a single standard. See also * OpenVera * e * SystemC *SystemVerilog *Property Specification Language Property Specification Language (PSL) is a temporal logic extending linear temporal logic with a range of operators for both ease of expression and enhancement of expressive power. PSL makes an extensive use of regular expressions and syntactic su ... References ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Test Bench
A test bench or testing workbench is an environment used to verify the correctness or soundness of a design or model. The term has its roots in the testing of electronic devices, where an engineer would sit at a lab bench with tools for measurement and manipulation, such as oscilloscopes, multimeters, soldering irons, wire cutters, and so on, and manually verify the correctness of the device under test (DUT). In the context of software or firmware or hardware engineering, a test bench is an environment in which the product under development is tested with the aid of software and hardware tools. The software may need to be modified slightly in some cases to work with the test bench but careful coding can ensure that the changes can be undone easily and without introducing bugs. The term "test bench" is used in digital design with a hardware description language to describe the test code, which instantiates the DUT and runs the test. An additional meaning for "test bench" is an i ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Specman
Specman is an EDA tool that provides advanced automated functional verification of hardware designs. It provides an environment for working with, compiling, and debugging testbench environments written in the ''e'' Hardware Verification Language. Specman also offers automated testbench generation to boost productivity in the context of block, chip, and system verification. The Specman tool itself does not include an HDL-simulator (for design languages such as VHDL or Verilog.) To simulate an e-testbench with a design written in VHDL/Verilog, Specman must be run in conjunction with a separate HDL simulation tool. Specman is a feature of Cadence new Xcelium simulator, where tighter product integration offers both faster runtime performance and debug capabilities not available with other HDL-simulators. In principle, Specman can co-simulate with any HDL-simulator supporting standard PLI or VHPI interface, such as Synopsys's VCS, or Mentor's Questa. History Specman was originally d ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Design Automation Conference
The Design Automation Conference, or DAC, is an annual event, a combination of a technical conference and a trade show, both specializing in electronic design automation (EDA). DAC is the oldest and largest conference in EDA, started in 1964. It grew out of the SHARE ("Society to Help Avoid Redundant Effort") design automation workshop. Its originators Marie Pistilli and Pasquale (Pat) Pistilli were honored by the EDA community. Pat received the highest honor in EDA industry, the Phil Kaufman Award, for this effort and Marie was honored by having an award established in her name, the Marie Pistilli Award. Up until the mid-'70s, DAC had sessions on all types of design automation, including mechanical and architectural. After that, for all intents and purposes, only topics concerned with electronic design have been included. Also until the mid-'70s, DAC was strictly a technical conference. Then a few companies started to request space to show their products, and within a few ye ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Cadence Design Systems
Cadence Design Systems, Inc. (stylized as cādence), headquartered in San Jose, California, is an American multinational corporation, multinational computational software company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, Electronic hardware, hardware and silicon structures for designing integrated circuits, System on chip, systems on chips (SoCs) and printed circuit boards. History Origins Cadence Design Systems began as an Electronic design automation, electronic design automation (EDA) company, formed by the 1988 merger of Solomon Design Automation (SDA), co-founded in 1983 by A. Richard Newton, Richard Newton, Alberto Sangiovanni-Vincentelli and James Solomon, and ECAD, Inc., ECAD, a public company co-founded by Ping Chao, Glen Antle and Paul Huang in 1982. SDA's CEO Joseph Costello (software executive), Joseph Costello was appointed as CEO of the newly combined company. Executive leadership Following the resignation of Cadenc ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Aspect-oriented Programming
In computing, aspect-oriented programming (AOP) is a programming paradigm that aims to increase modularity by allowing the separation of cross-cutting concerns. It does so by adding behavior to existing code (an advice) ''without'' modifying the code itself, instead separately specifying which code is modified via a "pointcut" specification, such as "log all function calls when the function's name begins with 'set. This allows behaviors that are not central to the business logic (such as logging) to be added to a program without cluttering the code core to the functionality. AOP includes programming methods and tools that support the modularization of concerns at the level of the source code, while aspect-oriented software development refers to a whole engineering discipline. Aspect-oriented programming entails breaking down program logic into distinct parts (so-called ''concerns'', cohesive areas of functionality). Nearly all programming paradigms support some level of groupi ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Universal Verification Methodology
The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM ( Open Verification Methodology) which was, to a large part, based on the eRM (e Reuse Methodology) for the e Verification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor Graphics, Synopsys, Xilinx Simulator(XSIM). History In December 2009, a technical subcommittee of Accellera — a standards organization in the electronic design automation (EDA) industry — voted to establish the UVM and decided to base this new standard on the Open Verification Methodology (OVM-2.1.1), a verification methodology de ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Object-oriented Programming
Object-oriented programming (OOP) is a programming paradigm based on the concept of "objects", which can contain data and code. The data is in the form of fields (often known as attributes or ''properties''), and the code is in the form of procedures (often known as ''methods''). A common feature of objects is that procedures (or methods) are attached to them and can access and modify the object's data fields. In this brand of OOP, there is usually a special name such as or used to refer to the current object. In OOP, computer programs are designed by making them out of objects that interact with one another. OOP languages are diverse, but the most popular ones are class-based, meaning that objects are instances of classes, which also determine their types. Many of the most widely used programming languages (such as C++, Java, Python, etc.) are multi-paradigm and they support object-oriented programming to a greater or lesser degree, typically in combination with imper ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
VHDL
The VHSIC Hardware Description Language (VHDL) is a hardware description language (HDL) that can model the behavior and structure of digital systems at multiple levels of abstraction, ranging from the system level down to that of logic gates, for design entry, documentation, and verification purposes. Since 1987, VHDL has been standardized by the Institute of Electrical and Electronics Engineers (IEEE) as IEEE Std 1076; the latest version of which is IEEE Std 1076-2019. To model analog and mixed-signal systems, an IEEE-standardized HDL based on VHDL called VHDL-AMS (officially IEEE 1076.1) has been developed. VHDL is named after the United States Department of Defense program that created it, the Very High-Speed Integrated Circuits Program (VHSIC). In the early 1980s, the VHSIC Program sought a new HDL for use in the design of the integrated circuits it aimed to develop. The product of this effort was VHDL Version 7.2, released in 1985. The effo ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Verilog
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits, as well as in the design of genetic circuits. In 2009, the Verilog standard (IEEE 1364-2005) was merged into the SystemVerilog standard, creating IEEE Standard 1800-2009. Since then, Verilog is officially part of the SystemVerilog language. The current version is IEEE standard 1800-2017. Overview Hardware description languages such as Verilog are similar to software programming languages because they include ways of describing the propagation time and signal strengths (sensitivity). There are two types of assignment operators; a blocking assignment (=), and a non-blocking (>>. A generate–endgenerate construct (similar to VHDL's generate–endgenerate) allows Verilog ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
