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Advanced Microcontroller Bus Architecture
The ARM Advanced Microcontroller Bus Architecture (AMBA) is an open-standard, on-chip interconnect specification for the connection and management of functional blocks in system-on-a-chip (SoC) designs. It facilitates development of multi-processor designs with large numbers of controllers and components with a bus architecture. Since its inception, the scope of AMBA has, despite its name, gone far beyond microcontroller devices. Today, AMBA is widely used on a range of ASIC and SoC parts including applications processors used in modern portable mobile devices like smartphones. AMBA is a registered trademark of ARM Ltd. AMBA was introduced by ARM in 1996. The first AMBA buses were the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). In its second version, AMBA 2 in 1999, ARM added AMBA High-performance Bus (AHB) that is a single clock-edge protocol. In 2003, ARM introduced the third generation, AMBA 3, including Advanced eXtensible Interface (AXI) to reach even ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Functional Unit
In computer engineering, an execution unit (E-unit or EU) is a part of the central processing unit (CPU) that performs the operations and calculations as instructed by the computer program. It may have its own internal control sequence unit (not to be confused with the CPU's main control unit), some registers, and other internal units such as an arithmetic logic unit (ALU), address generation unit (AGU), floating-point unit (FPU), load-store unit (LSU), branch execution unit (BEU) or some smaller and more specific components. archived on the |
SDRAM
Synchronous dynamic random-access memory (synchronous dynamic RAM or SDRAM) is any DRAM where the operation of its external pin interface is coordinated by an externally supplied clock signal. DRAM integrated circuits (ICs) produced from the early 1970s to early 1990s used an ''asynchronous'' interface, in which input control signals have a direct effect on internal functions only delayed by the trip across its semiconductor pathways. SDRAM has a ''synchronous'' interface, whereby changes on control inputs are recognised after a rising edge of its clock input. In SDRAM families standardized by JEDEC, the clock signal controls the stepping of an internal finite-state machine that responds to incoming commands. These commands can be pipelined to improve performance, with previously started operations completing while new commands are received. The memory is divided into several equally sized but independent sections called ''banks'', allowing the device to operate on a memory a ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Altera
Altera Corporation was a manufacturer of programmable logic devices (PLDs) headquartered in San Jose, California. It was founded in 1983 and acquired by Intel in 2015. The main product lines from Altera were the flagship Stratix series, mid-range Arria series, and lower-cost Cyclone series system on a chip field-programmable gate arrays (FPGAs); the MAX series complex programmable logic device and non-volatile FPGAs; Quartus design software; and Enpirion PowerSoC DC-DC power solutions. The company was founded in 1983 by semiconductor veterans Rodney Smith, Robert Hartmann, James Sansbury, and Paul Newhagen with $500,000 in seed money. The name of the company was a play on "alterable", the type of chips the company created. In 1984, the company formed a long-running design partnership with Intel, and 1988, became a public company via an initial public offering. In 1994, Altera acquired the PLD business of Intel for $50 million. On December 28, 2015, the company was acquired by ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Nios II
Nios II is a 32-bit embedded processor architecture designed specifically for the Altera family of field-programmable gate array (FPGA) integrated circuits. Nios II incorporates many enhancements over the original Nios architecture, making it more suitable for a wider range of embedded computing applications, from digital signal processing (DSP) to system-control. Nios II is a successor to Altera's first configurable 16-bit embedded processor Nios, introduced in 2000. Key features Like the original Nios, the Nios II architecture is a RISC soft-core architecture which is implemented entirely in the programmable logic and memory blocks of Altera FPGAs. Unlike its predecessor it is a full 32-bit design: * 32 general-purpose 32-bit registers, * Full 32-bit instruction set, data path, and address space, * Single-instruction 32 × 32 multiply and divide producing a 32-bit result. The soft-core nature of the Nios II processor lets the system designer specify and generate a custom Ni ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Integrated Device Technology
Integrated Device Technology, Inc., is an American corporation headquartered in San Jose, California, that designs, manufactures, and markets low-power, high-performance mixed-signal semiconductor solutions for the advanced communications, computing, and consumer industries. The company markets its products primarily to original equipment manufacturers (OEMs). Founded in 1980, the company began as a provider of complementary metal-oxide semiconductors (CMOS) for the communications business segment and computing business segments. The company is focused on three major areas: communications infrastructure (wireless and wired), high-performance computing, and advanced power management. Business segments The communications segment offers communication clocks, serial RapidIO solutions for wireless base station infrastructure applications, radio frequency products, digital logic products, first-in and first-out (FIFO) memories, integrated communications processors, static random-acc ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
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