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CoreConnect is a
microprocessor
A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circ ...
bus
A bus (contracted from omnibus, with variants multibus, motorbus, autobus, etc.) is a road vehicle that carries significantly more passengers than an average car or van. It is most commonly used in public transport, but is also in use for cha ...
-architecture from
IBM for
system-on-a-chip
A system on a chip or system-on-chip (SoC ; pl. ''SoCs'' ) is an integrated circuit that integrates most or all components of a computer or other electronic system. These components almost always include a central processing unit (CPU), memory ...
(SoC) designs. It was designed to ease the integration and reuse of processor, system, and peripheral
cores within standard and custom SoC designs. As a standard SoC
design point, it serves as the foundation of IBM or non-IBM devices. Elements of this architecture include the processor local bus (PLB), the on-chip peripheral bus (OPB), a bus bridge, and a
device control register (DCR) bus. High-performance peripherals connect to the high-
bandwidth
Bandwidth commonly refers to:
* Bandwidth (signal processing) or ''analog bandwidth'', ''frequency bandwidth'', or ''radio bandwidth'', a measure of the width of a frequency range
* Bandwidth (computing), the rate of data transfer, bit rate or thr ...
, low-
latency PLB. Slower peripheral cores connect to the OPB, which reduces traffic on the PLB. CoreConnect has bridging capabilities to the competing
AMBA bus architecture, allowing reuse of existing SoC-components.
IBM makes the CoreConnect bus available as a no-fee, no-royalty architecture to tool-vendors, core IP-companies, and chip-development companies. As such it is licensed by over 1500 electronics companies such as
Cadence
In Western musical theory, a cadence (Latin ''cadentia'', "a falling") is the end of a phrase in which the melody or harmony creates a sense of full or partial resolution, especially in music of the 16th century onwards.Don Michael Randel (199 ...
,
Ericsson
(lit. "Telephone Stock Company of LM Ericsson"), commonly known as Ericsson, is a Swedish multinational networking and telecommunications company headquartered in Stockholm. The company sells infrastructure, software, and services in informa ...
,
Lucent
Lucent Technologies, Inc. was an American multinational telecommunications equipment company headquartered in Murray Hill, New Jersey. It was established on September 30, 1996, through the divestiture of the former AT&T Technologies business u ...
,
Nokia
Nokia Corporation (natively Nokia Oyj, referred to as Nokia) is a Finnish multinational telecommunications, information technology, and consumer electronics corporation, established in 1865. Nokia's main headquarters are in Espoo, Finland, i ...
,
Siemens and
Synopsys
Synopsys is an American electronic design automation (EDA) company that focuses on silicon design and verification, silicon intellectual property and software security and quality. Products include tools for logic synthesis and physical de ...
.
The CoreConnect is an integral part of IBM's embedded offerings and is used extensively in their
PowerPC 4x0 based designs. In the past,
Xilinx
Xilinx, Inc. ( ) was an American technology and semiconductor company that primarily supplied programmable logic devices. The company was known for inventing the first commercially viable field-programmable gate array (FPGA) and creating the ...
was using CoreConnect as the infrastructure for all of their embedded processor designs.
Processor Local Bus (PLB)
*General processor local bus
*Synchronous, nonmultiplexed bus
*Separate Read, Write data buses
*Supports concurrent Read, Writes
*Multimaster, programmable-priority, arbitrated bus
*32-bit up to 64-bit address
*32-/64-/128-bit implementations (to 256-bit)
*66/133/183 MHz (32-/64-/128-bit)
*Pipelined, supports early split transactions
*Overlapped arbitration (last cycle)
*Supports fixed, variable-length bursts
*Bus locking
*High bandwidth capabilities, up to 2.9
GB/s.
On-chip Peripheral Bus (OPB)
*Peripheral bus for slower devices
*Synchronous, nonmultiplexed bus
*Multimaster, arbitrated bus
*Up to a 64-bit address bus
*Separate 32-bit Read, Write buses
*Pipelined transactions
*Overlapped arbitration (last cycle)
*Supports bursts
*Dynamic bus sizing, 8-, 16-, 32-bit devices
*Single-cycle data transfers
*Bus locking (parking)
Device Control Register (DCR) bus
This bus:
* provides fully
synchronous
Synchronization is the coordination of events to operate a system in unison. For example, the conductor of an orchestra keeps the orchestra synchronized or ''in time''. Systems that operate with all parts in synchrony are said to be synchronou ...
movement of
GPR data between
CPU and slave logic
* functions as a synchronous, nonmultiplexed bus
* has separate buses to read and to write data
* consists of a single-master, multiple-slave bus
* includes a 10-bit address bus
* features 32-bit data buses
* uses two-cycle minimum Read/Write cycles
* utilizes distributed multiplexer architecture
* supports 8-, 16-, and 32-bit devices
* performs single-cycle data transfers
External links
CoreConnect bus architecture, IBM.comCoreConnect Technology , Xilinx.comCoreConnect: The On-Chip Bus System, ElectronicDesign.comDevice Control Register Bus 3.5 Architecture Specifications
{{Computer-bus
Computer buses
IBM computer hardware