Depletion-mode

Enhancement-load and depletion-load logic families

Depletion-load NMOS logic refers to the logic family that became dominant in silicon VLSI in the latter half of the 1970s; the process supported both enhancement-mode and depletion-mode transistors, and typical logic circuits used enhancement-mode devices as pull-down switches and depletion-mode devices as loads, or pull-ups. Logic families built in older processes that did not support depletion-mode transistors were retrospectively referred to as enhancement-load logic, or as saturated-load logic, since the enhancement-mode transistors were typically connected with gate to the V_DD supply and operated in the saturation region (sometimes the gates are biased to a higher V_GG voltage and operated in the linear region, for a better power–delay product (PDP), but the loads then take more area). Alternatively, rather than static logic gates, dynamic logic such as four-phase logic was sometimes used in processes that did not have depletion-mode transistors available.