Grounded-gate NMOS, commonly known as ggNMOS, is an

electrostatic discharge Electrostatic discharge (ESD) is a sudden and momentary flow of electric current between two differently-charged objects when brought close together or when the dielectric between them breaks down, often creating a visible electric spark, spark as ...

(ESD) protection device used within

CMOS Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss ", , ) is a type of MOSFET, metal–oxide–semiconductor field-effect transistor (MOSFET) semiconductor device fabrication, fabrication process that uses complementary an ...

integrated circuits An integrated circuit (IC), also known as a microchip or simply chip, is a set of electronic circuits, consisting of various electronic components (such as transistors, resistors, and capacitors) and their interconnections. These components a ...

(ICs). Such devices are used to protect the inputs and outputs of an IC, which can be accessed off-chip ( wire-bonded to the pins of a package or directly to a

printed circuit board A printed circuit board (PCB), also called printed wiring board (PWB), is a Lamination, laminated sandwich structure of electrical conduction, conductive and Insulator (electricity), insulating layers, each with a pattern of traces, planes ...

) and are therefore subject to ESD when touched. An ESD event can deliver a large amount of energy to the chip, potentially destroying input/output circuitry; a ggNMOS device or other ESD protective devices provide a safe path for current to flow, instead of through more sensitive circuitry. ESD protection by means of such devices or other techniques is important to product reliability: 35% of all IC failures in the field are associated with ESD damage.

Structure

As the name implies, a ggNMOS device consists of a relatively wide NMOS device in which the gate, source, and body are tied together to ground. The drain of the ggNMOS is connected to the I/O pad under protection. A

parasitic Parasitism is a close relationship between species, where one organism, the parasite, lives (at least some of the time) on or inside another organism, the host, causing it some harm, and is adapted structurally to this way of life. The ent ...

NPN

bipolar junction transistor A bipolar junction transistor (BJT) is a type of transistor that uses both electrons and electron holes as charge carriers. In contrast, a unipolar transistor, such as a field-effect transistor (FET), uses only one kind of charge carrier. A ...

(BJT) is thus formed with the drain ( n-type) acting as the collector, the base/source combination (n-type) as the emitter, and the

substrate Substrate may refer to: Physical layers *Substrate (biology), the natural environment in which an organism lives, or the surface or medium on which an organism grows or is attached ** Substrate (aquatic environment), the earthy material that exi ...

( p-type) as the base. As is explained below, a key element to the operation of the ggNMOS is the parasitic resistance present between the emitter and base terminals of the parasitic npn BJT. This resistance is a result of the finite conductivity of the p-type doped substrate.

Operation

When a positive ESD event appears upon the I/O pad (drain), the collector-base junction of the parasitic NPN BJT becomes reverse biased to the point of

avalanche breakdown Avalanche breakdown (or the avalanche effect) is a phenomenon that can occur in both insulating and semiconducting materials. It is a form of electric current multiplication that can allow very large currents within materials which are otherwis ...

. At this point, the positive current flowing from the base to ground induces a voltage potential across the parasitic resistor, causing a positive voltage to appear across the base-emitter junction. The positive V_BE forward biases this junction, triggering the parasitic NPN BJT.

References

{{reflist, refs= {{cite conference , title = ESD design methodology , last1 = Issaq , first1 = E. , last2 = Merri , first2 = R. , date = 1993 , pages = 223-237 , location = Lake Buena Vista, Florida , conference = Electrical Overstress/Electrostatic Discharge Symposium {{cite conference , title = A review of EOS/ESD field failures in military equipment , last1 = Green , first1 = T. , date = 1988 , pages = 7-14 , location = Anaheim, California , conference = Electrical Overstress/Electrostatic Discharge Symposium {{cite book , last=Wang, first=Albert, date=2002, title=On-Chip ESD Protection for Integrated Circuits: An IC Design Perspective, location=Norwell, MA, USA, publisher=Kluwer Academic Publishing, isbn=0792376471 https://www.researchgate.net/publication/4133911_Modeling_MOS_snapback_for_circuit-level_ESD_simulation_using_BSIM3_and_VBIC_models Semiconductor devices MOSFETs