Advanced Vector Extensions (AVX) are extensions to the x86

instruction set architecture In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an ...

for

microprocessor A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circu ...

s from

Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the devel ...

and

Advanced Micro Devices Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. While it initially manufa ...

(AMD). They were proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge processor shipping in Q1 2011 and later by AMD with the

Bulldozer A bulldozer or dozer (also called a crawler) is a large, motorized machine equipped with a metal blade to the front for pushing material: soil, sand, snow, rubble, or rock during construction work. It travels most commonly on continuous trac ...

processor shipping in Q3 2011. AVX provides new features, new instructions and a new coding scheme. AVX2 (also known as Haswell New Instructions) expands most integer commands to 256 bits and introduces new instructions. They were first supported by Intel with the Haswell processor, which shipped in 2013.

AVX-512 AVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture (ISA) proposed by Intel in July 2013, and implemented in Intel's Xeon Phi x200 (Knights Landing) and Skylake-X CPUs; ...

expands AVX to 512-bit support using a new

EVEX prefix The EVEX prefix (enhanced vector extension) and corresponding coding scheme is an extension to the 32-bit x86 (IA-32) and 64-bit x86-64 (AMD64) instruction set architecture. EVEX is based on, but should not be confused with the MVEX prefix used by ...

encoding proposed by Intel in July 2013 and first supported by Intel with the

Knights Landing Knights Landing (formerly, Baltimore and East Grafton) is a census-designated place in Yolo County, California, United States, founded by William Knight. It is located on the Sacramento River around 25 miles northwest of Sacramento in the northeas ...

co-processor, which shipped in 2016. In conventional processors, AVX-512 was introduced with

Skylake Skylake or Sky Lake may refer to: * Skylake (microarchitecture), the codename for a processor microarchitecture developed by Intel as the successor to Broadwell * Skylake (Mysia), a town of ancient Mysia, now in Turkey * Sky Lake, Florida Sky La ...

server and HEDT processors in 2017.

Advanced Vector Extensions

AVX uses sixteen YMM registers to perform a single instruction on multiple pieces of data (see

SIMD Single instruction, multiple data (SIMD) is a type of parallel processing in Flynn's taxonomy. SIMD can be internal (part of the hardware design) and it can be directly accessible through an instruction set architecture (ISA), but it should ...

). Each YMM register can hold and do simultaneous operations (math) on: * eight 32-bit single-precision floating point numbers or * four 64-bit double-precision floating point numbers. The width of the SIMD registers is increased from 128 bits to 256 bits, and renamed from XMM0–XMM7 to YMM0–YMM7 (in

x86-64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging ...

mode, from XMM0–XMM15 to YMM0–YMM15). The legacy SSE instructions can be still utilized via the VEX prefix to operate on the lower 128 bits of the YMM registers. AVX introduces a three-operand SIMD instruction format called VEX coding scheme, where the destination register is distinct from the two source operands. For example, an SSE instruction using the conventional two-operand form can now use a non-destructive three-operand form , preserving both source operands. Originally, AVX's three-operand format was limited to the instructions with SIMD operands (YMM), and did not include instructions with general purpose registers (e.g. EAX). It was later used for coding new instructions on general purpose registers in later extensions, such as BMI. VEX coding is also used for instructions operating on the k0-k7 mask registers that were introduced with

. The alignment requirement of SIMD memory operands is relaxed. Unlike their non-VEX coded counterparts, most VEX coded vector instructions no longer require their memory operands to be aligned to the vector size. Notably, the VMOVDQA instruction still requires its memory operand to be aligned. The new VEX coding scheme introduces a new set of code prefixes that extends the

opcode In computing, an opcode (abbreviated from operation code, also known as instruction machine code, instruction code, instruction syllable, instruction parcel or opstring) is the portion of a machine language instruction that specifies the opera ...

space, allows instructions to have more than two operands, and allows SIMD vector registers to be longer than 128 bits. The VEX prefix can also be used on the legacy SSE instructions giving them a three-operand form, and making them interact more efficiently with AVX instructions without the need for VZEROUPPER and VZEROALL. The AVX instructions support both 128-bit and 256-bit SIMD. The 128-bit versions can be useful to improve old code without needing to widen the vectorization, and avoid the penalty of going from SSE to AVX, they are also faster on some early AMD implementations of AVX. This mode is sometimes known as AVX-128.

New instructions

These AVX instructions are in addition to the ones that are 256-bit extensions of the legacy 128-bit SSE instructions; most are usable on both 128-bit and 256-bit operands.

CPUs with AVX

** Sandy Bridge processors, Q1 2011 ** Sandy Bridge E processors, Q4 2011 ** Ivy Bridge processors, Q1 2012 ** Ivy Bridge E processors, Q3 2013 ** Haswell processors, Q2 2013 ** Haswell E processors, Q3 2014 ** Broadwell processors, Q4 2014 **

processors, Q3 2015 ** Broadwell E processors, Q2 2016 ** Kaby Lake processors, Q3 2016 (ULV mobile)/Q1 2017 (desktop/mobile) ** Skylake-X processors, Q2 2017 ** Coffee Lake processors, Q4 2017 ** Cannon Lake processors, Q2 2018 **

Whiskey Lake Whiskey Lake is Intel's codename for a family of third 14 nm generation Skylake low-power mobile processors. Intel announced Whiskey Lake on August 28, 2018. Changes * 14++ nm process, same as Coffee Lake * Increased turbo clocks (300� ...

processors, Q3 2018 ** Cascade Lake processors, Q4 2018 ** Ice Lake processors, Q3 2019 ** Comet Lake processors (only Core and Xeon branded), Q3 2019 ** Tiger Lake (Core, Pentium and Celeron branded) processors, Q3 2020 ** Rocket Lake processors, Q1 2021 ** Alder Lake (Xeon, Core, Pentium and Celeron branded) processors, Q4 2021. Supported both in Golden Cove P-cores and

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E-cores. ** Raptor Lake ** Meteor Lake ** Arrow Lake ** Lunar Lake Not all CPUs from the listed families support AVX. Generally, CPUs with the commercial denomination Core i3/i5/i7/i9 support them, whereas Pentium and Celeron CPUs before Tiger Lake do not. * AMD: ** Jaguar-based processors and newer ** Puma-based processors and newer ** "Heavy Equipment" processors *** Bulldozer-based processors, Q4 2011 *** Piledriver-based processors, Q4 2012 *** Steamroller-based processors, Q1 2014 *** Excavator-based processors and newer, 2015 ** Zen-based processors, Q1 2017 ** Zen+-based processors, Q2 2018 ** Zen 2-based processors, Q3 2019 ** Zen 3 processors, Q4 2020 **

Zen 4 Zen 4 is the codename for a CPU microarchitecture by AMD, released on September 27, 2022. It is the successor to Zen 3 and uses TSMC's N5 process for CCDs. Zen 4 powers Ryzen 7000 mainstream desktop processors (codenamed "Raphael") and wi ...

processors, Q4 2022 Issues regarding compatibility between future Intel and AMD processors are discussed under XOP instruction set. * VIA: ** Nano QuadCore ** Eden X4 * Zhaoxin: ** WuDaoKou-based processors (KX-5000 and KH-20000)

Compiler and assembler support

* Absoft supports with - flag. * The Free Pascal compiler supports AVX and AVX2 with the -CfAVX and -CfAVX2 switches from version 2.7.1. * RAD studio (v11.0 Alexandria) supports AVX2 and AVX512. * The

GNU Assembler The GNU Assembler, commonly known as gas or as, is the assembler developed by the GNU Project. It is the default back-end of GCC. It is used to assemble the GNU operating system and the Linux kernel, and various other software. It is a part o ...

(GAS) inline assembly functions support these instructions (accessible via GCC), as do Intel primitives and the Intel inline assembler (closely compatible to GAS, although more general in its handling of local references within inline code). * GCC starting with version 4.6 (although there was a 4.3 branch with certain support) and the Intel Compiler Suite starting with version 11.1 support AVX. * The Open64 compiler version 4.5.1 supports AVX with - flag. * PathScale supports via the - flag. * The Vector Pascal compiler supports AVX via the - flag. * The Visual Studio 2010/

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compiler supports AVX via intrinsic and switch. * Other assemblers such as

MASM The Microsoft Macro Assembler (MASM) is an x86 assembler that uses the Intel syntax for MS-DOS and Microsoft Windows. Beginning with MASM 8.0, there are two versions of the assembler: One for 16-bit & 32-bit assembly sources, and another (ML64 ...

VS2010 version, YASM,

FASM FASM (''flat assembler'') is an assembler for x86 processors. It supports Intel-style assembly language on the IA-32 and x86-64 computer architectures. It claims high speed, size optimizations, operating system (OS) portability, and macro a ...

, NASM and JWASM.

Operating system support

AVX adds new register-state through the 256-bit wide YMM register file, so explicit

operating system An operating system (OS) is system software that manages computer hardware, software resources, and provides common daemon (computing), services for computer programs. Time-sharing operating systems scheduler (computing), schedule tasks for ef ...

support is required to properly save and restore AVX's expanded registers between

context switch In computing, a context switch is the process of storing the state of a process or thread, so that it can be restored and resume execution at a later point, and then restoring a different, previously saved, state. This allows multiple processes ...

es. The following operating system versions support AVX: *

DragonFly BSD DragonFly BSD is a free and open-source Unix-like operating system forked from FreeBSD 4.8. Matthew Dillon, an Amiga developer in the late 1980s and early 1990s and FreeBSD developer between 1994 and 2003, began working on DragonFly BSD in ...

: support added in early 2013. *

FreeBSD FreeBSD is a free and open-source Unix-like operating system descended from the Berkeley Software Distribution (BSD), which was based on Research Unix. The first version of FreeBSD was released in 1993. In 2005, FreeBSD was the most popular ...

: support added in a patch submitted on January 21, 2012, which was included in the 9.1 stable release *

Linux Linux ( or ) is a family of open-source Unix-like operating systems based on the Linux kernel, an operating system kernel first released on September 17, 1991, by Linus Torvalds. Linux is typically packaged as a Linux distribution, which i ...

: supported since kernel version 2.6.30, released on June 9, 2009. *

macOS macOS (; previously OS X and originally Mac OS X) is a Unix operating system developed and marketed by Apple Inc. since 2001. It is the primary operating system for Apple's Mac (computer), Mac computers. Within the market of ...

: support added in 10.6.8 (

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) update released on June 23, 2011. *

OpenBSD OpenBSD is a security-focused operating system, security-focused, free and open-source, Unix-like operating system based on the Berkeley Software Distribution (BSD). Theo de Raadt created OpenBSD in 1995 by fork (software development), forking N ...

: support added on March 21, 2015. * Solaris: supported in Solaris 10 Update 10 and Solaris 11 *

Windows Windows is a group of several proprietary graphical operating system families developed and marketed by Microsoft. Each family caters to a certain sector of the computing industry. For example, Windows NT for consumers, Windows Server for ...

: supported in

Windows 7 Windows 7 is a major release of the Windows NT operating system developed by Microsoft. It was released to manufacturing on July 22, 2009, and became generally available on October 22, 2009. It is the successor to Windows Vista, released nearl ...

SP1,

Windows Server 2008 R2 Windows Server 2008 R2 is the fifth version of the Windows Server operating system produced by Microsoft and released as part of the Windows NT family of operating systems. It was released to manufacturing on July 22, 2009, and became generally ...

SP1,

Windows 8 Windows 8 is a major release of the Windows NT operating system developed by Microsoft. It was released to manufacturing on August 1, 2012; it was subsequently made available for download via MSDN and TechNet on August 15, 2012, and later to ...

Windows 10 Windows 10 is a major release of Microsoft's Windows NT operating system. It is the direct successor to Windows 8.1, which was released nearly two years earlier. It was released to manufacturing on July 15, 2015, and later to retail on ...

** Windows Server 2008 R2 SP1 with Hyper-V requires a hotfix to support AMD AVX (Opteron 6200 and 4200 series) processors
KB2568088

Advanced Vector Extensions 2

Advanced Vector Extensions 2 (AVX2), also known as Haswell New Instructions, is an expansion of the AVX instruction set introduced in Intel's Haswell microarchitecture. AVX2 makes the following additions: * expansion of most vector integer SSE and AVX instructions to 256 bits *

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support, enabling vector elements to be loaded from non-contiguous memory locations * DWORD- and QWORD-granularity any-to-any permutes * vector shifts. Sometimes three-operand fused multiply-accumulate (FMA3) extension is considered part of AVX2, as it was introduced by Intel in the same processor microarchitecture. This is a separate extension using its own CPUID flag and is described on its own page and not below.

New instructions

CPUs with AVX2

** Haswell processors (only Core and Xeon branded), Q2 2013 ** Haswell E processors, Q3 2014 ** Broadwell processors, Q4 2014 ** Broadwell E processors, Q3 2016 **

processors, Q3 2015 ** Kaby Lake processors, Q3 2016 (ULV mobile)/Q1 2017 (desktop/mobile) ** Skylake-X processors, Q2 2017 ** Coffee Lake processors, Q4 2017 ** Cannon Lake processors, Q2 2018 ** Cascade Lake processors, Q2 2019 ** Ice Lake processors, Q3 2019 ** Comet Lake processors, Q3 2019 ** Tiger Lake (Core, Pentium and Celeron branded) processors, Q3 2020 ** Rocket Lake processors, Q1 2021 ** Alder Lake (Xeon, Core, Pentium and Celeron branded) processors, Q4 2021. Supported both in Golden Cove P-cores and

E-cores. ** Raptor Lake ** Meteor Lake ** Arrow Lake ** Lunar Lake * AMD ** **

Excavator Excavators are heavy construction equipment consisting of a boom, dipper (or stick), bucket and cab on a rotating platform known as the "house". The house sits atop an undercarriage with tracks or wheels. They are a natural progression fr ...

processor and newer, Q2 2015 **

Zen Zen ( zh, t=禪, p=Chán; ja, text= 禅, translit=zen; ko, text=선, translit=Seon; vi, text=Thiền) is a school of Mahayana Buddhism that originated in China during the Tang dynasty, known as the Chan School (''Chánzong'' 禪宗), and ...

processors, Q1 2017 ** Zen+ processors, Q2 2018 ** Zen 2 processors, Q3 2019 ** Zen 3 processors, Q4 2020 **

processors, Q4 2022 * VIA: ** Nano QuadCore ** Eden X4

AVX-512

''AVX-512'' are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture proposed by

in July 2013, and are supported with Intel's

processor. AVX-512 instruction are encoded with the new

. It allows 4 operands, 8 new 64-bit opmask registers, scalar memory mode with automatic broadcast, explicit rounding control, and compressed displacement memory

addressing mode Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how the machine language instructions ...

. The width of the register file is increased to 512 bits and total register count increased to 32 (registers ZMM0-ZMM31) in x86-64 mode. AVX-512 consists of multiple extensions not all meant to be supported by all processors implementing them. The instruction set consists of the following: * AVX-512 Foundation (F) adds several new instructions and expands most 32-bit and 64-bit floating point SSE-SSE4.1 and AVX/AVX2 instructions with EVEX coding scheme to support the 512-bit registers, operation masks, parameter broadcasting, and embedded rounding and exception control * AVX-512 Conflict Detection Instructions (CD) efficient conflict detection to allow more loops to be vectorized, supported by Knights Landing * AVX-512 Exponential and Reciprocal Instructions (ER) exponential and reciprocal operations designed to help implement transcendental operations, supported by Knights Landing * AVX-512 Prefetch Instructions (PF) new prefetch capabilities, supported by Knights Landing * AVX-512 Vector Length Extensions (VL) extends most AVX-512 operations to also operate on XMM (128-bit) and YMM (256-bit) registers (including XMM16-XMM31 and YMM16-YMM31 in x86-64 mode) * AVX-512 Byte and Word Instructions (BW) extends AVX-512 to cover 8-bit and 16-bit integer operations * AVX-512 Doubleword and Quadword Instructions (DQ) enhanced 32-bit and 64-bit integer operations * AVX-512 Integer

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(IFMA) fused multiply add for 512-bit integers. * AVX-512 Vector Byte Manipulation Instructions (VBMI) adds vector byte permutation instructions which are not present in AVX-512BW. * AVX-512 Vector Neural Network Instructions Word variable precision (4VNNIW) vector instructions for deep learning. * AVX-512 Fused Multiply Accumulation Packed Single precision (4FMAPS) vector instructions for deep learning. * VPOPCNTDQ count of bits set to 1. * VPCLMULQDQ carry-less multiplication of quadwords. * AVX-512 Vector Neural Network Instructions (VNNI) vector instructions for deep learning. * AVX-512 Galois Field New Instructions (GFNI) vector instructions for calculating Galois field. * AVX-512 Vector AES instructions (VAES) vector instructions for

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coding. * AVX-512 Vector Byte Manipulation Instructions 2 (VBMI2) byte/word load, store and concatenation with shift. * AVX-512 Bit Algorithms (BITALG) byte/word bit manipulation instructions expanding VPOPCNTDQ. * AVX-512

Bfloat16 The bfloat16 (Brain Floating Point) floating-point format is a computer number format occupying 16 bits in computer memory; it represents a wide dynamic range of numeric values by using a floating radix point. This format is a truncated (16-b ...

Floating-Point Instructions (BF16) vector instructions for AI acceleration. * AVX-512

Half-Precision In computing, half precision (sometimes called FP16) is a binary floating-point computer number format that occupies 16 bits (two bytes in modern computers) in computer memory. It is intended for storage of floating-point values in applications wh ...

Floating-Point Instructions (FP16) vector instructions for operating on floating-point and complex numbers with reduced precision. Only the core extension AVX-512F (AVX-512 Foundation) is required by all implementations, though all current processors also support CD (conflict detection);