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PIIX3
PCI IDE ISA Xcelerator (PIIX), also known as Intel 82371, is a family of Intel southbridge (computing), southbridge Integrated circuit, microchips employed in some Intel chipsets. x86 virtualization implementations often support emulations of various PIIX-based chipsets. Versions PIIX The PIIX integrated an Advanced Technology Attachment, IDE controller with two Intel 8237, 8237 Direct memory access, DMA controllers, the Intel 8253, 8254 Programmable Interval Timer, PIT, and two Intel 8259, 8259 Programmable Interrupt Controller, PICs and a Conventional PCI, PCI to Industry Standard Architecture, ISA bus bridge. It was introduced with the 430FX Triton chipset in 1995. The mobile version was introduced with the 430MX mobile Triton chipset. The following variations existed: *82371FB (PIIX) *82371MX (MPIIX) Mobile PIIX3 The PIIX3 introduced a Universal Serial Bus, USB 1.0 controller and support for an external Intel APIC Architecture, I/O APIC. It was used with the Intel 430HX, 430H ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Intel 440FX
The Intel 440FX (codenamed Natoma), is a chipset from Intel, supporting the Pentium Pro and Pentium II processors. It is the first chipset from Intel that supports Pentium II. It is also known as i440FX and was released in May 1996. Official part numbers include the 82441FX and the 82442FX. 440FX does not support UltraDMA, SDRAM, or AGP. Its southbridge counterpart is the PIIX3. It was replaced by Intel 440LX. The designers of the QEMU emulator originally chose to simulate this chipset and its counterpart PIIX3. See also * PCI bus bridges * List of Intel chipsets References External linksIntel 440FX ("Natoma") 440FX
The Intel 440FX (codenamed Natoma), is a chipset from Intel, supporting the Pentium Pro ...
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Intel 430HX
The Intel 430HX (codenamed Triton II) is a chipset from Intel, supporting Socket 7 processors, including the Pentium and Pentium MMX. It is also known as i430HX and it was released in February 1996. The official part number is 82430HX. Features The 430HX chipset had all the features of the 430FX (Triton I) plus support for ECC, parity RAM, two-way SMP, USB, and then current PCI to improve speed. It consists of one 82439HX TXC, the northbridge and one PIIX3, the southbridge. The 430HX chipset supported up to 512MB of RAM (64MB or 512MB cacheable depending on tag RAM size). Limitations Not all 430HX boards allowed for tag RAM expansion, only allowing 64MB cacheable; 430HX also did not support the then-new SDRAM memory technology. Dual-voltage support, for Pentium MMX or AMD K6 CPUs, was also not mandatory on 430HX boards, requiring the use of an interposer to step down the voltage. See also * List of Intel chipsets This article provides a list of motherboard chipsets made ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Intel APIC Architecture
In computing, Intel's Advanced Programmable Interrupt Controller (APIC) is a family of interrupt controllers. As its name suggests, the APIC is more advanced than Intel's 8259 Programmable Interrupt Controller (PIC), particularly enabling the construction of multiprocessor systems. It is one of several architectural designs intended to solve interrupt routing efficiency issues in multiprocessor computer systems. The APIC is a split architecture design, with a local component (LAPIC) usually integrated into the processor itself, and an optional I/O APIC on a system bus. The first APIC was the 82489DX it was a discrete chip that functioned both as local and I/O APIC. The 82489DX enabled construction of symmetric multiprocessor (SMP) systems with the Intel 486 and early Pentium processors; for example, the reference two-way 486 SMP system used three 82489DX chips, two as local APICs and one as I/O APIC. Starting with the P54C processor, the local APIC functionality was integrate ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
List Of Intel Chipsets
This article provides a list of motherboard chipsets made by Intel, divided into three main categories: those that use the PCI bus for interconnection (the 4xx series), those that connect using specialized "hub links" (the 8xx series), and those that connect using PCI Express (the 9xx series). The chipsets are listed in chronological order. Pre-chipset situation An earlier chipset support for Intel 8085 microprocessor can be found at MCS-85 family section. Early IBM XT-compatible mainboards did not have a chipset yet, but relied instead on a collection of discrete TTL chips by Intel: * the 8284 clock generator * the 8288 bus controller * the 8254 Programmable Interval Timer * the 8255 parallel I/O interface * the 8259 Programmable Interrupt Controller * the 8237 DMA controller Early chipsets To integrate the functions needed on a mainboard into a smaller amount of ICs, Intel licensed the ZyMOS POACH chipset for its Intel 80286 and Intel 80386SX processors (the ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Universal Serial Bus
Universal Serial Bus (USB) is an industry standard that establishes specifications for cables, connectors and protocols for connection, communication and power supply ( interfacing) between computers, peripherals and other computers. A broad variety of USB hardware exists, including 14 different connector types, of which USB-C is the most recent and the only one not currently deprecated. First released in 1996, the USB standards are maintained by the USB Implementers Forum (USB-IF). The four generations of USB are: USB 1.''x'', USB 2.0, USB 3.''x'', and USB4. Overview USB was designed to standardize the connection of peripherals to personal computers, both to communicate with and to supply electric power. It has largely replaced interfaces such as serial ports and parallel ports, and has become commonplace on a wide range of devices. Examples of peripherals that are connected via USB include computer keyboards and mice, video cameras, printers, portable media pla ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Southbridge (computing)
The southbridge is one of the two chips in the core logic chipset on a personal computer (PC) motherboard, the other being the northbridge. The southbridge typically implements the slower capabilities of the motherboard in a northbridge/southbridge chipset computer architecture. In systems with Intel chipsets, the southbridge is named I/O Controller Hub (ICH), while AMD has named its southbridge Fusion Controller Hub (FCH) since the introduction of its Fusion AMD Accelerated Processing Unit (APU) while moving the functions of the Northbridge onto the CPU die, hence making it similar in function to the Platform hub controller. The southbridge can usually be distinguished from the northbridge by not being directly connected to the CPU. Rather, the northbridge ties the southbridge to the CPU. Through the use of controller integrated channel circuitry, the northbridge can directly link signals from the I/O units to the CPU for data control and access. Current status Due to th ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Super I/O
Super I/O is a class of I/O controller integrated circuits that began to be used on personal computer motherboards in the late 1980s, originally as add-in cards, later embedded on the motherboards. A super I/O chip combines interfaces for a variety of low- bandwidth devices. Now it is mostly merged with EC. The functions below are usually provided by the super I/O if they are on the motherboard: * A floppy-disk controller * An IEEE 1284-compatible parallel port (commonly used for printers) * One or more 16C550-compatible serial port UARTs * Keyboard controller for PS/2 keyboard and/or mouse Most Super I/O chips include some additional low-speed devices, such as: * Temperature, voltage, and fan speed interface * Thermal Zone * Chassis intrusion detection * Mainboard power management * LED management * PWM fan speed control * An IrDA Port controller * A game port (not provided by recent super I/O chips anymore because Windows XP is the last Windows OS to support a game ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
I/O Controller Hub
I/O Controller Hub (ICH) is a family of Intel southbridge microchips used to manage data communications between a CPU and a motherboard, specifically Intel chipsets based on the Intel Hub Architecture. It is designed to be paired with a second support chip known as a northbridge. As with any other southbridge, the ICH is used to connect and control peripheral devices. As CPU speeds increased data transmission between the CPU and support chipset, the support chipset eventually emerged as a bottleneck between the processor and the motherboard. Accordingly, starting with the Intel 5 Series, a new architecture was used that incorporated some functions of the traditional north and south bridge chips onto the CPU itself, with the remaining functions being consolidated into a single Platform Controller Hub (PCH). This replaces the traditional two chip setup. ICH The first version of the ICH was released in June 1999 along with the Intel 810 northbridge. While its predecessor, ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
System Controller Hub
System Controller Hub (SCH) is a family of Intel microchips employed in chipsets for low-power Atom-based platforms. Its architecture is consistent with the Intel Hub Architecture but combines the traditional northbridge and southbridge functions into a single microchip. Poulsbo Poulsbo is the codename of the first SCH and plays a key role in Intel's second-generation Menlow UMPC and MID platform chipset for Atom Silverthorne microprocessors. The graphics core is called GMA 500 and unlike most graphics cores used by Intel was developed by Imagination Technologies. Intel licensed the PowerVR SGX 535 as a graphics core and the PowerVR VXD370 for H.264/MPEG-4 AVC playback. The video core is able to process 720p as well as 1080i resolutions. This has the following variations: SCH UL11LSCH US15LSCH US15WSCH US15WPSCH US15WPTSCH US15X GMA 500 Linux support Although several netbooks using the Poulsbo chipset are shipped with some distribution of Linux (notably the Sony Vaio ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Platform Controller Hub
The Platform Controller Hub (PCH) is a family of Intel's single-chip chipsets, first introduced in 2009. It is the successor to the Intel Hub Architecture, which used two chips - a northbridge and southbridge, and first appeared in the Intel 5 Series. The PCH controls certain data paths and support functions used in conjunction with Intel CPUs. These include clocking (the system clock), Flexible Display Interface (FDI) and Direct Media Interface (DMI), although FDI is used only when the chipset is required to support a processor with integrated graphics. As such, I/O functions are reassigned between this new central hub and the CPU compared to the previous architecture: some northbridge functions, the memory controller and PCIe lanes, were integrated into the CPU while the PCH took over the remaining functions in addition to the traditional roles of the southbridge. AMD has its equivalent for the PCH, known simply as a chipset, no longer using the previous term Fusion control ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Itanium
Itanium ( ) is a discontinued family of 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64). Launched in June 2001, Intel marketed the processors for enterprise servers and high-performance computing systems. The Itanium architecture originated at Hewlett-Packard (HP), and was later jointly developed by HP and Intel. Itanium-based systems were produced by HP/Hewlett Packard Enterprise (HPE) (the HPE Integrity Servers line) and several other manufacturers. In 2008, Itanium was the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, Power ISA, and SPARC. In February 2017, Intel released the final generation, Kittson, to test customers, and in May began shipping in volume. It was used exclusively in mission-critical servers from Hewlett Packard Enterprise. In 2019, Intel announced that new orders for Itanium would be accepted until January 30, 2020, and shipments would cease by July ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Intel 440BX
The Intel 440BX (codenamed Seattle) is a chipset from Intel, supporting Pentium II, Pentium III, and Celeron processors. It is also known as the i440BX and was released in April 1998. The official part number is 82443BX. Features The 440BX originally supported Slot 1 and later Socket 370 Intel P6-based processors in single and SMP configurations at speeds of up to 1 GHz (and potentially up to 1.4 GHz with certain unsupported modifications, up to 1.7 GHz can be achieved using Front Side Bus speeds higher than 133 MHz and appropriate cooling). Its southbridge counterpart is the PIIX4E. History The Intel 440BX is the third Pentium II chipset released by Intel, succeeding the 440FX and 440LX. With the new 100 MHz front side bus, Pentium II CPUs were able to scale better in performance by reducing the difference between processor clock and bus speed. The previous 66 MHz bus had become a serious bottleneck and dated back to the first Pentium " ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
