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MOVDDUP
In the x86 assembly programming language, MOVDDUP is the name for a specific action performable by modern x86 processors with 3rd-generation Streaming SIMD Extensions (SSE3). This action involves copying a number to temporary space in the processor for use in other computations. Specifically, MOVDDUP causes one, double-precision, floating-point source to be copied to both the lower half and upper half of an XMM register. Usage The source operand can be either an XMM register (''xmm2'') or a memory address (''m64''). When the source operand is an XMM register, the lower half of the register is used in the operation. When the source operand is a memory address, it is assumed to be the address of an 8-byte region, the value at which is used in the operation. The destination operand must be an XMM register (''xmm1''). Potential exceptions References *{{mono, gcc info documentation. *''Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Refere ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
MOVAPD
In the x86 assembly programming language, MOVAPD is the name for a specific action performable by modern x86 processors with 2nd-generation Streaming SIMD Extensions (SSE2). This action involves copying a pair of numbers to temporary space in the processor for use in other computations. MOVAPD is one of the fastest ways to accomplish this effect - it is faster than the comparable instruction MOVSD. Specifically, MOVAPD causes a 16-byte-aligned packed- doubles source to be copied to an XMM register or a 16-byte memory region. Usage The source operand can be either an XMM register (''xmm2'') or a memory address (''m128''). The destination operand can be either an XMM register (''xmm1'') or a memory address (''m128''). Note, however, that the source and destination operands cannot both be memory addresses. Potential Exceptions If a memory address operand is not 16-byte-aligned, a general protection exception (#GP) will be raised. This can cause strange interoperability bugs whe ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
X86 Instruction Listings
The x86 instruction set refers to the set of instructions that x86-compatible microprocessors support. The instructions are usually part of an executable program, often stored as a computer file and executed on the processor. The x86 instruction set has been extended several times, introducing wider Register (computing), registers and datatypes as well as new functionality. x86 integer instructions Below is the full 8086/8088 instruction set of Intel (81 instructions total). Most if not all of these instructions are available in 32-bit mode; they just operate on 32-bit registers (eax, ebx, etc.) and values instead of their 16-bit (ax, bx, etc.) counterparts. The updated instruction set is also grouped according to architecture (i386, i486, i686) and more generally is referred to as (32-bit) x86 and (64-bit) x86-64 (also known as AMD64). Original 8086/8088 instructions Added in specific Intel processors Added with Intel 80186, 80186/Intel 80188, 80188 Added with ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
MOVHPD
In the x86 assembly programming language, MOVHPD is the name for a specific action performable by modern x86 processors with 2nd-generation Streaming SIMD Extensions (SSE2). This action involves either copying a number from memory to temporary space or copying a number from temporary space to memory. Specifically, MOVHPD causes the value at an 8-byte memory region to be either copied to or assigned from the upper half of an XMM register. Usage The source operand can be either an XMM register (''xmm'') or a memory address (''m64''). When the source operand is an XMM register, the destination operand must be a memory address. When the source operand is a memory address, the destination operand must be an XMM register. Note that the lower half of the XMM register is unaffected by this operation. Potential exceptions References *'' {{mono, info page.'' *''Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M'', November, 2006. S ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revision of their Pentium 4 CPU. In April 2005, AMD introduced a subset of SSE3 in revision E (Venice and San Diego) of their Athlon 64 CPUs. The earlier SIMD instruction sets on the x86 platform, from oldest to newest, are MMX, 3DNow! (developed by AMD, but not supported by Intel processors), SSE, and SSE2. SSE3 contains 13 new instructions over SSE2. Changes The most notable change is the capability to work horizontally in a register, as opposed to the more or less strictly vertical operation of all previous SSE instructions. More specifically, instructions to add and subtract the multiple values stored within a single register have been added. These instructions can be used to speed up the implementation of a number of DSP and ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |