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Intel Chipsets
This article provides a list of motherboard chipsets made by Intel, divided into three main categories: those that use the Peripheral Component Interconnect, PCI bus for interconnection (the 4xx series), those that connect using specialized "hub links" (the 8xx series), and those that connect using PCI Express (the 9xx series). The chipsets are listed in chronological order. Pre-chipset situation An earlier chipset support for Intel 8085 microprocessor can be found at Intel 8085#MCS-85 family, MCS-85 family section. Early IBM XT-compatible motherboard, mainboards did not yet have a chipset, but relied instead on a collection of discrete transistor–transistor logic, TTL chips by Intel: * the Intel 8284, 8284 clock generator * the Intel 8288, 8288 bus controller * the Intel 8254, 8254 programmable interval timer * the Intel 8255, 8255 parallel I/O interface * the Intel 8259, 8259 programmable interrupt controller * the Intel 8237, 8237 DMA controller Early chipsets To integr ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Pentium E2220 With Intel I945GC Chipset
Pentium is a series of x86 architecture-compatible microprocessors produced by Intel from 1993 to 2023. The Pentium (original), original Pentium was Intel's fifth generation processor, succeeding the i486; Pentium was Intel's flagship processor line for over a decade until the introduction of the Intel Core line in 2006. Pentium-branded processors released from 2009 onwards were considered entry-level products positioned above the low-end Intel Atom, Atom and Celeron series, but below the faster Core lineup and workstation/server Xeon series. The later Pentiums, which have little more than their name in common with earlier Pentiums, were based on both the architecture used in Atom and that of Core processors. In the case of Atom architectures, Pentiums were the highest performance implementations of the architecture. Pentium processors with Core architectures prior to 2017 were distinguished from the faster, higher-end i-series processors by lower clock rates and disabling ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ZyMOS
ZyMOS Corporation (its name a partial acronym for Zirconium Metal Oxide Semiconductors), later Appian Technology, Inc., was a semiconductor manufacturing company located in Sunnyvale, California. It initially designed and manufactured custom and semi-custom integrated circuits. After the introduction of the IBM PC in the early 1980s, there was strong customer demand for ICs to support the production of IBM PC-AT clones. In 1987, Appian responded to this demand by developing the POACH (PC-On-A-Chip) peripheral series, one of the first chipsets of its kind, enabling manufacturers of PC AT clones to simplify PC motherboard designs and reduce cost and time to market. Intel soon licensed this chipset to support Intel 80286 sales. Intel second-sourced to Zymos Corp. of these 82230/82231 High Integration AT-Compatible Chip Set.Ormsby, John, Editor, "New Product Focus: Components: Intel's 82X3X Chip-set Handles Logic Functions That Once Required The Services Of Sources Of Chips", In ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Non-maskable Interrupt
In computing, a non-maskable interrupt (NMI) is a hardware interrupt that standard interrupt-masking techniques in the system cannot ignore. It typically occurs to signal attention for non-recoverable hardware errors. Some NMIs may be masked, but only by using proprietary methods specific to the particular NMI. With regard to SPARC, the non-maskable interrupt (NMI), despite having the highest priority among interrupts, can be prevented from occurring through the use of an interrupt mask. An NMI is often used when response time is critical or when an interrupt should never be disabled during normal system operation. Such uses include reporting non-recoverable hardware errors, system debugging and profiling, and handling of special cases like system resets. Modern computer architectures typically use NMIs to handle non-recoverable errors which need immediate attention. Therefore, such interrupts should not be masked in the normal operation of the system. These errors include non-r ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Programmable Interrupt Controller
In computing, a programmable interrupt controller (PIC) is an integrated circuit that helps a microprocessor (or CPU) handle interrupt requests (IRQs) coming from multiple different sources (like external I/O devices) which may occur simultaneously. It helps prioritize IRQs so that the CPU switches execution to the most appropriate interrupt handler (ISR) after the PIC assesses the IRQs' relative priorities. Common modes of interrupt priority include hard priorities, rotating priorities, and cascading priorities. PICs often allow mapping input to outputs in a configurable way. On the PC architecture PIC are typically embedded into a southbridge chip whose internal architecture is defined by the chipset vendor's standards. Common features PICs typically have a common set of registers: interrupt request register (IRR), in-service register (ISR), and interrupt mask register (IMR). The IRR specifies which interrupts are pending acknowledgement, and is typically a symbolic regist ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Direct Memory Access
Direct memory access (DMA) is a feature of computer systems that allows certain hardware subsystems to access main system computer memory, memory independently of the central processing unit (CPU). Without DMA, when the CPU is using programmed input/output, it is typically fully occupied for the entire duration of the read or write operation, and is thus unavailable to perform other work. With DMA, the CPU first initiates the transfer, then it does other operations while the transfer is in progress, and it finally receives an interrupt from the DMA controller (DMAC) when the operation is done. This feature is useful at any time that the CPU cannot keep up with the rate of data transfer, or when the CPU needs to perform work while waiting for a relatively slow I/O data transfer. Many hardware systems use DMA, including disk drive controllers, graphics cards, network cards and sound cards. DMA is also used for intra-chip data transfer in some multi-core processors. Computers that h ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Intel 80486SL
The Intel i486SL is the power-saving variant of the i486DX microprocessor. The SL was designed for use in mobile computers. It was produced between November 1992 and June 1993. Clock speeds available were 20, 25 and 33 MHz. The i486SL contained all features of the i486DX. This version performed more than twice and consumes 50% less power than the Intel386 SL version. In addition, the System Management Mode (SMM) (the same mode introduced with i386SL) was included with this processor. The system management mode makes it possible to shut down the processor without losing data. To achieve this, the processor state is saved in an area of static RAM (SMRAM). The 3.3-volt 25 MHz version of Intel486 SL which contains 1.4 million-transistor device built using the 800 nm of three-layer CHMOS V process. This was available for USD $269 in 1,000-unit quantities.Chen, Allan, "On the Air and on the Road", Intel Corporation, Microcomputer Solutions, January/February 1993. page 2 In m ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
80386SL
The Intel 386, originally released as the 80386 and later renamed i386, is the third-generation x86 architecture microprocessor from Intel. It was the first 32-bit processor in the line, making it a significant evolution in the x86 architecture. Pre-production samples of the 386 were released to select developers in 1985, while mass production commenced in 1986. The 386 was the central processing unit (CPU) of many workstations and high-end personal computers of the time. The 386 began to fall out of public use starting with the release of the i486 processor in 1989, while in embedded systems the 386 remained in widespread use until Intel finally discontinued it in 2007. Compared to its predecessor the Intel 80286 ("286"), the 80386 added a three-stage instruction pipeline which it brings up to total of 6-stage instruction pipeline, extended the architecture from 16-bits to 32-bits, and added an on-chip memory management unit. This paging translation unit made it much easier ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
I486
The Intel 486, officially named i486 and also known as 80486, is a microprocessor introduced in 1989. It is a higher-performance follow-up to the i386, Intel 386. It represents the fourth generation of binary compatible CPUs following the Intel 8086, 8086 of 1978, the Intel 80286 of 1982, and 1985's i386. It was the first tightly-instruction pipeline, pipelined x86 design as well as the first x86 chip to include more than one million transistors. It offered a large on-chip Cache (computing), cache and an integrated floating-point unit. When it was announced, the initial performance was originally published between 15 and 20 VAX Unit of Performance, VAX MIPS, between 37,000 and 49,000 Dhrystone, dhrystones per second, and between 6.1 and 8.2 double-precision Whetstone (benchmark), megawhetstones per second for both 25 and 33 MHz version. A typical 50 MHz i486 executes 41 million instructions per second Dhrystone MIPS and SPECint, SPEC integer rating of 27.9.Chen, ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Micro Channel Architecture
Micro Channel architecture, or the Micro Channel bus, is a proprietary hardware, proprietary 16-bit computing, 16- or 32-bit computing, 32-bit parallel communication, parallel computer bus (computing), bus publicly introduced by IBM in 1987 which was used on IBM PS/2, PS/2 and other computers until the mid-1990s. Its name is commonly abbreviated as "MCA", although not by IBM. In IBM products, it superseded the Industry Standard Architecture, ISA bus and was itself subsequently superseded by the Peripheral Component Interconnect, PCI bus architecture. Background The development of Micro Channel was driven by both technical and business pressures. Technology The IBM AT bus, which later became known as the Industry Standard Architecture (ISA) bus, had a number of technical design limitations, including: * A slow bus speed. * A limited number of interrupts, fixed in hardware. * A limited number of I/O device addresses, also fixed in hardware. * Hardwired and complex configur ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Parallel Port
In computing, a parallel port is a type of interface found on early computers ( personal and otherwise) for connecting peripherals. The name refers to the way the data is sent; parallel ports send multiple bits of data at once (parallel communication), as opposed to serial communication, in which bits are sent one at a time. To do this, parallel ports require multiple data lines in their cables and port connectors and tend to be larger than contemporary serial ports, which only require one data line. There are many types of parallel ports, but the term has become most closely associated with the printer port or Centronics port found on most personal computers from the 1970s through the 2000s. It was an industry ''de facto'' standard for many years, and was finally standardized as IEEE 1284 in the late 1990s, which defined the Enhanced Parallel Port (EPP) and Extended Capability Port (ECP) bi-directional versions. Today, the parallel port interface is virtually non ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Universal Asynchronous Receiver/transmitter
A universal asynchronous receiver-transmitter (UART ) is a peripheral device for asynchronous serial communication in which the data format and transmission speeds are configurable. It sends data bits one by one, from the least significant to the most significant, framed by start and stop bits so that precise timing is handled by the communication channel. The electric signaling levels are handled by a driver circuit external to the UART. Common signal levels are RS-232, RS-485, and raw TTL for short debugging links. Early teletypewriters used current loops. It was one of the earliest computer communication devices, used to attach teletypewriters for an operator console. It was also an early hardware system for the Internet. A UART is usually implemented in an integrated circuit (IC) and used for serial communications over a computer or peripheral device serial port. One or more UART peripherals are commonly integrated in microcontroller chips. Specialised UARTs are used for ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Floppy Disk Controller
A floppy-disk controller (FDC) is a hardware component that directs and controls reading from and writing to a computer's floppy disk drive (FDD). It has evolved from a discrete set of components on one or more circuit boards to a special-purpose integrated circuit (IC or "chip") or a component thereof. An FDC is responsible for reading data presented from the host computer and converting it to the drive's on-disk format using one of a number of encoding schemes, like FM encoding (single density) or MFM encoding (double density), and reading those formats and returning it to its original binary values. Depending on the platform, data transfers between the controller and host computer would be controlled by the computer's own microprocessor, or an inexpensive dedicated microprocessor like the MOS 6507 or Zilog Z80. Early controllers required additional circuitry to perform specific tasks like providing clock signals and setting various options. Later designs included more of t ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
