The Z80 CPU is an
8-bit based microprocessor. It was introduced by
Zilog in 1976 as the startup company's first product. The Z80 was
Federico Faggin in late 1974 and developed by him and his
then-11 employees at
Zilog from early 1975 until March 1976, when the
first fully working samples were delivered. With the revenue from the
Z80, the company built its own chip factories and grew to over a
thousand employees over the following two years.
Zilog Z80 was a software-compatible extension and enhancement of
Intel 8080 and, like it, was mainly aimed at embedded systems.
According to the designers, the primary targets for the Z80 CPU (and
its optional support and peripheral ICs) were products like
intelligent terminals, high end printers and advanced cash registers
as well as telecom equipment, industrial robots and other kinds of
automation equipment. The Z80 was officially introduced on the market
in July 1976 and came to be widely used also in general desktop
CP/M and other operating systems as well as in the
home computers of the 1980s. It was also common in military
applications, musical equipment, such as synthesizers, and in the
computerized coin operated video games of the late 1970s and early
1980, the arcade machines or video game arcade cabinets.
The Z80 was one of the most commonly used CPUs in the home computer
market from the late 1970s to the mid-1980s.
Zilog licensed the
Z80 to the US-based
Synertek and Mostek, which had helped them with
initial production, as well as to a European second source
manufacturer, SGS. The design was copied also by several Japanese,
East European and Russian manufacturers. This won the Z80
acceptance in the world market since large companies like NEC,
Toshiba, Sharp, and
Hitachi started to manufacture the device (or
their own Z80-compatible clones or designs). In recent decades Zilog
has refocused on the ever-growing market for embedded systems (for
which the original Z80 and the
Z180 were designed) and the most recent
Z80-compatible microcontroller family, the fully pipelined
with a linear 16 MB address range, has been successfully
introduced alongside the simpler
Z180 and Z80 products.
2.1 Programming model and register set
2.2 Z80 assembly language
Datapoint 2200 and
2.2.2 New syntax
Instruction set and encoding
2.3.1 Undocumented instructions
2.4 Example code
2.5 Instruction execution
2.6 Compatible peripherals
3 Second sources and derivatives
3.1 Second sources
4 Notable uses
4.1 Desktop computers
Embedded systems and consumer electronics
4.2.2 Consumer electronics
4.2.3 Musical instruments
5 See also
8 Further reading
9 External links
Photo of the original
Zilog Z80 microprocessor design in
depletion-load nMOS. Total die size is 3545×3350 µm. (This
actual chip manufactured in 1990.)
The Z80's original DIP40 chip package pinout
The Z80 came about when physicist
Federico Faggin left
Intel at the
end of 1974 to found
Zilog with Ralph Ungermann. At Fairchild
Semiconductor, and later at Intel, Faggin had been working on
fundamental transistor and semiconductor manufacturing technology. He
also developed the basic design methodology used for memories and
Intel and led the work on the
Intel 4004, the 8080
and several other ICs. Masatoshi Shima, the principal logic and
transistor level-designer of the 4004 and the
8080 under Faggin's
supervision, also joined the
By March 1976,
Zilog had developed the Z80 as well as an accompanying
assembler based development system for its customers, and by July
1976, this was formally launched onto the market. (Some of the Z80
support and peripheral ICs were under development at this point, and
many of them were launched during the following year.)
Early Z80s were manufactured by
Synertek and Mostek, before
its own manufacturing factory ready, in late 1976. These companies
were chosen because they could do the ion implantation needed to
create the depletion-mode MOSFETs that the Z80 design used as load
transistors in order to cope with a single 5 Volt power supply.
Faggin designed the instruction set to be binary compatible with the
Intel 8080 so that most
8080 code, notably the
system and Intel's
PL/M compiler for
8080 (as well as its generated
code), would run unmodified on the new Z80 CPU. Masatoshi Shima
designed most of the microarchitecture as well as the gate and
transistor levels of the Z80 CPU, assisted by a small number of
engineers and layout people. CEO
Federico Faggin was actually
heavily involved in the chip layout work, together with two dedicated
layout people. Faggin worked 80 hours a week in order to meet the
tight schedule given by the financial investors, according to
The Z80 offered many improvements over the 8080:
An enhanced instruction set including single-bit addressing,
shifts/rotates on memory and registers other than the accumulator,
rotate instructions for BCD number strings in memory, program looping,
program counter relative jumps, block copy, block input/output (I/O),
and byte search instructions. The Z80 also incorporated an
overflow flag and had better support for signed 8- and 16-bit
New IX and IY index registers with instructions for direct base+offset
A better interrupt system
A more automatic and general vectorized interrupt system, mode 2,
primarily intended for Zilog's line of counter/timers, DMA and
communications controllers, as well as a fixed vector interrupt
system, mode 1, for simple systems with minimal hardware (with mode 0
being the 8080-compatible mode).
A non maskable interrupt (NMI) which can be used to respond to power
down situations or other high priority events (and allowing a
minimalistic Z80 system to easily implement a two-level interrupt
scheme in mode 1).
Two separate register files, which could be quickly switched, to speed
up response to interrupts such as fast asynchronous event handlers or
a multitasking dispatcher. Although they were not intended as extra
registers for general code, they were nevertheless used that way in
Less hardware required for power supply, clock generation and
interface to memory and I/O
Single 5-volt power supply (the
-5 V/+5 V/+12 V).
Single-phase 5 V clock (the
8080 needed a high-amplitude (9 to 12
volt) non-overlapping two-phase clock).
DRAM refresh mechanism that would otherwise have to be
provided by external circuitry.
Non-multiplexed buses (the
8080 had state-signals multiplexed onto the
A special reset function which clears only the program counter so that
a single Z80 CPU could be used in a development system such as an
The Z80 took over from the
8080 and its offspring, the 8085, in the
processor market, and became one of the most popular 8-bit
CPUs. Perhaps a key to the initial success of the Z80 was the
DRAM refresh, and other features which allowed systems to be
built with fewer support chips (Z80 embedded systems typically use
static RAM and hence do not need this refresh).
For the original NMOS design, the specified upper clock frequency
limit increased successively from the introductory 2.5 MHz, via
the well known 4 MHz (Z80A), up to 6 (Z80B) and 8 MHz
CMOS versions were also developed with specified upper
frequency limits ranging from 4 MHz up to 20 MHz for the
version sold today. The
CMOS versions also allowed low-power sleep
with internal state retained, having no lower frequency limit. The
fully compatible derivatives HD64180/Z180 and eZ80 are
currently specified for up to 33 and 50 MHz respectively.
Programming model and register set
An approximate block diagram of the Z80. There is no dedicated adder
for offsets or separate incrementer for R, and no need for more than a
single 16-bit temporary register WZ (although the incrementer latches
are also used as a 16-bit temporary register, in other contexts). It
is the PC and IR registers that are placed in a separate group, with a
detachable bus segment, to allow updates of these registers in
parallel with the main register bank.
The programming model and register set are fairly conventional,
ultimately based on the register structure of the Datapoint 2200
(which the related
8086 family also inherited). The Z80 was designed
as an extension of the 8080, created by the same engineers, which in
turn was an extension of the 8008. The
8008 was basically a PMOS
implementation of the TTL-based CPU of the Datapoint 2200.
This original design allowed register H and L to be paired into a
16-bit address register HL In the
8080 this pairing was
generalized into BC and DE, while HL also became usable as a 16-bit
8080 also introduced the important
data mode for accumulator operations and immediate 16-bit data for HL,
BC and DE loads. Furthermore, direct 16-bit copying between HL and
memory was now possible, using a direct address. The Z80
orthogonalized this a bit further by making all 16-bit register pairs
(including IX and IY) more general purpose, with 16-bit copying
directly to and from memory.
The 16-bit IX and IY registers in the Z80 are primarily intended as
base address-registers, where a particular instruction supplies a
constant offset, but they are also usable as 16-bit accumulators,
among other things. The Z80 also introduces a new signed overflow flag
and complements the fairly simple 16-bit arithmetics of the
dedicated instructions for signed 16-bit arithmetics.
8080 compatible registers AF, BC, DE, HL are duplicated as two
separate banks in the Z80, where the processor can quickly switch
from one bank to the other; a feature useful for speeding up
responses to single-level, high-priority interrupts. A similar feature
was present in the
Datapoint 2200 but was never implemented at Intel.
The dual register-set makes sense as the Z80 (like most
microprocessors at the time) was really intended for embedded use, not
for personal computers, or the yet-to-be invented home computers.
According to one of the designers, Masatoshi Shima, the market focus
was on high performance printers, high-end cash registers, and
intelligent terminals, although Ralph Ungermann also saw other
opportunities, such as computers. The two register sets also
turned out to be quite useful for heavily optimized manual
assembly-language coding, such as for floating point arithmetics or
home computer games.
The Z80 registers
AF (accumulator and flags)
HL (indirect address)
AF' (accumulator and flags)
HL' (indirect address)
As on the 8080,
8-bit registers are typically paired to provide 16-bit
8080 compatible registers are:
8-bit accumulator (A) and flag bits (F) carry, zero, minus,
parity/overflow, half-carry (used for BCD), and an Add/Subtract flag
(usually called N) also for BCD
BC: 16-bit data/address register or two
DE: 16-bit data/address register or two
HL: 16-bit accumulator/address register or two
SP: stack pointer, 16 bits
PC: program counter, 16 bits
The new registers introduced with the Z80 are:
IX: 16-bit index or base register for
8-bit immediate offsets or two
IY: 16-bit index or base register for
8-bit immediate offsets or two
I: interrupt vector base register, 8 bits
DRAM refresh counter, 8 bits (msb does not count)
AF': alternate (or shadow) accumulator and flags (toggled in and out
with EX AF,AF' )
BC', DE' and HL': alternate (or shadow) registers (toggled in and out
Four bits of interrupt status and interrupt mode status
There is no direct access to the alternate registers; instead, two
special instructions, EX AF,AF' and EXX, each toggles one of two
multiplexer flip-flops. This enables fast context switches for
interrupt service routines: EX AF, AF' may be used alone, for really
simple and fast interrupt routines, or together with EXX to swap the
whole BC, DE, HL set. This is still several times as fast as pushing
the same registers on the stack. Slower, lower priority, or multi
level interrupts normally use the stack to store registers, however.
The refresh register, R, increments each time the CPU fetches an
opcode (or opcode prefix) and has no simple relationship with program
execution. This has sometimes been used to generate pseudorandom
numbers in games, and also in software protection schemes.[citation
needed] It has also been employed as a "hardware" counter in some
designs; an example of this is the ZX81, which lets it keep track of
character positions on the TV screen by triggering an interrupt at
wrap around (by connecting INT to A6).
The interrupt vector register, I, is used for the Z80 specific mode 2
interrupts (selected by the IM 2 instruction). It supplies the high
byte of the base address for a 128-entry table of service routine
addresses which are selected via an index sent to the CPU during an
interrupt acknowledge cycle; this index is simply the low byte part of
the pointer to the tabulated indirect address pointing to the service
routine. The pointer identifies a particular peripheral chip or
peripheral function or event, where the chips are normally connected
in a so-called daisy chain for priority resolution. Like the refresh
register, this register has also sometimes been used creatively; in
interrupt modes 0 and 1 (or in a system not using interrupts) it can
be used as simply another
8-bit data register.
The instructions LD A,R and LD A,I affect the Z80 flags register,
unlike all the other LD (load) instructions. The Sign (bit 7) and Zero
(bit 6) flags are set according to the data loaded from the Refresh or
Interrupt source registers. For both instructions, the Parity/Overflow
flag (bit 2) is set according to the current state of the IFF2
Z80 assembly language
Datapoint 2200 and
8008 assembly language was based on a very simple (but
systematic) syntax inherited from the
Datapoint 2200 design. This
original syntax was later transformed into a new, somewhat more
traditional, assembly language form for this same original
At about the same time, the new assembly language was also extended to
accommodate the added addressing possibilities in the more advanced
Intel 8080 chip (the
8080 shared a language subset without
being binary compatible; however, the
8008 was binary compatible with
the Datapoint 2200).
In this process, the mnemonic L, for LOAD, was replaced by various
abbreviations of the words LOAD, STORE and MOVE, intermixed with other
symbolic letters. The mnemonic letter M, for memory (referenced by
HL), was lifted out from within the instruction mnemonic to become a
syntactically freestanding operand, while registers and combinations
of registers became very inconsistently denoted; either by abbreviated
operands (MVI D, LXI H and so on), within the instruction mnemonic
itself (LDA, LHLD and so on), or both at the same time (LDAX B, STAX D
and so on).
Datapoint 2200 & i8008
MOV byte ptr [BP],56
MOV byte ptr [DI+56],78
Illustration of four syntaxes, using samples of equivalent, or (for
8086) very similar, load and store instructions. The Z80 syntax
uses parentheses around an expression to indicate that the value
should be used as a memory address (as mentioned below), while the
8086 syntax uses brackets instead of ordinary parentheses for this
purpose. Both Z80 and
8086 use the + sign to indicate that a constant
is added to a base register to form an address
Intel claimed a copyright on their assembly mnemonics, a
new assembly syntax had to be developed for the Z80. This time a more
systematic approach was used:
All registers and register pairs are explicitly denoted by their full
Parentheses are consistently used to indicate "memory contents at"
(constant address or variable pointer dereferencing) with the
exception of some jump instructions.
All load and store instructions use the same mnemonic name, LD, for
LOAD (a return to the simplistic
Datapoint 2200 vocabulary); other
common instructions, such as ADD and INC, use the same mnemonic
regardless of addressing mode or operand size. This is possible
because the operands themselves carry enough information.
These principles made it straightforward to find names and forms for
all new Z80 instructions, as well as orthogonalizations of old ones,
such as LD BC,(1234).
Apart from naming differences, and despite a certain discrepancy in
basic register structure, the Z80 and
8086 syntax are virtually
isomorphic for a large portion of instructions. Only quite superficial
similarities (such as the word MOV, or the letter X, for extended
register) exist between the
8086 assembly languages, although
8080 programs can be assembled into
8086 object code using a special
assembler or translated to
8086 assembly language by a translator
Instruction set and encoding
The Z80 uses 252 out of the available 256 codes as single byte opcodes
("root instruction"); the four remaining codes are used extensively as
opcode prefixes: CB and ED enable extra instructions and DD or FD
selects IX+d or IY+d respectively (in some cases without displacement
d) in place of HL. This scheme gives the Z80 a large number of
permutations of instructions and registers;
Zilog categorizes these
into 158 different "instruction types", 78 of which are the same as
those of the
Intel 8080 (allowing operation of most
on a Z80). The
Zilog documentation further groups instructions into
the following categories:
8-bit arithmetic and logic operations
Bit set, reset, and test
Call, return, and restart
Exchange, block transfer, and search
General purpose arithmetic and CPU control
Input and output
Rotate and shift
No multiply instruction is available in the original Z80.
Different sizes and variants of additions, shifts, and rotates have
somewhat differing effects on flags because most of the
flag-changing properties of the
8080 were copied.
The Z80 has six new LD instructions that can load the DE, BC, and SP
register pairs from memory, and load memory from these three register
pairs—unlike the 8080. As on the 8080, load instructions do not
affect the flags (except for the special purpose I and R register
loads). A quirk (common with the 8080) of the register-to-register
load instructions is that each of the
8-bit registers can be loaded
from themselves (e.g. LD A,A). This is effectively a NOP.
Unlike the 8080, the Z80 can jump to a relative address using a signed
8-bit displacement. Only the Zero and Carry flags can be tested for
these new two-byte JR instructions.
A two-byte instruction specialized for program looping is new to the
Z80. DJNZ (Decrement Jump if Non-Zero) takes a signed 8-bit
displacement as an immediate operand. The B register is decremented.
If the result is nonzero then program execution jumps relative to the
address of the PC plus the displacement. The flags remain unaltered.
To perform an equivalent loop on an
8080 would require separate
decrement and jump (to a two-byte absolute address) instructions, and
the flag register would be altered.
The index register (IX/IY) instructions can be useful for accessing
data organised in fixed heterogenous structures (such as records) or
at fixed offsets relative a variable base address (as in recursive
stack frames) and can also reduce code size by removing the need for
multiple short instructions using non-indexed registers. However,
although they may save speed in some contexts when compared to
long/complex "equivalent" sequences of simpler operations, they incur
a lot of additional CPU time (e.g. 19 T-states to access one indexed
memory location vs. as little as 11 to access the same memory using HL
and INCrement it to point to the next). Thus, for simple or linear
accesses of data, IX and IY tend to be slower. Still, they may be
useful in cases where the 'main' registers are all occupied, by
removing the need to save/restore registers. Their officially
8-bit halves (see below) can be especially useful in this
context, for they incur less slowdown than their 16-bit parents.
Similarly, instructions for 16-bit additions are not particularly fast
(11 clocks) in the original Z80; nonetheless, they are about twice as
fast as performing the same calculations using
8-bit operations, and
equally important, they reduce register usage.
The 10-year-newer microcoded
Z180 design could initially afford more
"chip area", permitting a slightly more efficient implementation
(using a wider ALU, among other things); similar things can be said
for the Z800, Z280, and Z380. However, it was not until the fully
pipelined eZ80 was launched in 2001 that those instructions finally
became approximately as cycle-efficient as it is technically possible
to make them, i.e. given the Z80 encodings combined with the
capability to do an
8-bit read or write every clock cycle.[citation
The index registers, IX and IY, were intended as flexible 16 bit
pointers, enhancing the ability to manipulate memory, stack frames and
data structures. Officially, they were treated as 16-bit only. In
reality, they were implemented as a pair of
8-bit registers, in
the same fashion as the HL register, which is accessible either as 16
bits or separately as the High and Low registers. Even the binary
opcodes (machine language) were identical, but preceded by a new
Zilog published the opcodes and related mnemonics
for the intended functions, but did not document the fact that every
opcode that allowed manipulation of the H and L registers was equally
valid for the 8 bit portions of the IX and IY registers. As an
example, the opcode 26h followed by an immediate byte value (LD H,n)
will load that value into the H register. Preceding this two-byte
instruction with the IX register's opcode prefix, DD, would instead
result in the most significant 8 bits of the IX register being loaded
with that same value. A notable exception to this would be
instructions similar to LD H,(IX+d) which make use of both the HL and
IX or IY registers in the same instruction; in this case the DD
prefix is only applied to the (IX+d) portion of the instruction.
There are several other undocumented instructions as well.
Undocumented or illegal opcodes are not detected by the Z80 and have
various effects, some of which are useful. However, as they are not
part of the formal definition of the instruction set, different
implementations of the Z80 are not guaranteed to work the same way for
every undocumented opcode.
The OTDR instruction doesn't conform to the Z80 documentation. Both
OTDR and OTIR are supposed to leave the carry C unaffected. OTIR
functions correctly; however, during the execution of the OTDR
instruction, the carry takes the results of a spurious compare between
the accumulator and what has last been output by the OTDR instruction.
The following Z80 assembly source code is for a subroutine named
memcpy that copies a block of data bytes of a given size from one
location to another. Important: the example code does not handle a
certain case where the destination block overlaps the source; a fatal
bug. The sample code is extremely inefficient, intended to illustrate
various instruction types, rather than best practices for speed. In
particular, the Z80 has a single instruction that will execute the
entire loop (LDIR). The data block is copied one byte at a time, and
the data movement and looping logic utilizes 16-bit operations. Note
that the assembled code is binary-compatible with the
Intel 8080 and
1008 C3 00 10
; memcpy --
; Copy a block of memory from one location to another.
; Entry registers
; BC - Number of bytes to copy
; DE - Address of source data block
; HL - Address of target data block
; Return registers
; BC - Zero
org 1000h ;Origin at 1000h
loop ld a,b ;Test BC,
or c ;If BC = 0,
ret z ;Return
ld a,(de) ;Load A from (DE)
ld (hl),a ;Store A into (HL)
inc de ;Increment DE
inc hl ;Increment HL
dec bc ;Decrement BC
jp loop ;Repeat the loop
Each instruction is executed in steps that are usually termed machine
cycles (M-cycles), each of which can take between three and six clock
periods (T-cycles). Each M-cycle corresponds roughly to one memory
access or internal operation. Many instructions actually end during
the M1 of the next instruction which is known as a fetch/execute
Examples of typical instructions (R=read, W=write)
The Z80 machine cycles are sequenced by an internal state machine
which builds each M-cycle out of 3, 4, 5 or 6 T-cycles depending on
context. This avoids cumbersome asynchronous logic and makes the
control signals behave consistently at a wide range of clock
frequencies. It also means that a higher frequency crystal must be
used than without this subdivision of machine cycles (approximately
2–3 times higher). It does not imply tighter requirements on memory
access times, since a high resolution clock allows more precise
control of memory timings and so memory can be active in parallel with
the CPU to a greater extent, allowing more efficient use of available
memory bandwidth.
One central example of this is that, for opcode fetch, the Z80
combines two full clock cycles into a memory access period (the
M1-signal). In the Z80 this signal lasts for a relatively larger part
of the typical instruction execution time than in a design such as the
6800, 6502, or similar, where this period would typically last
typically 30-40% of a clock cycle. With memory chip
affordability (i.e. access times around 450-250 ns in the
1980s) typically determining the fastest possible
access time, this meant that such designs were locked to a
significantly longer clock cycle (i.e. lower internal clock speed)
than the Z80.
Memory was generally slow compared to the state machine sub-cycles
(clock cycles) used in contemporary microprocessors. The shortest
machine cycle that could safely be used in embedded designs has
therefore often been limited by memory access times, not by the
maximum CPU frequency (especially so during the home computer era).
However, this relation has slowly changed during the last decades,
particularly regarding SRAM; cacheless, single-cycle designs such as
the eZ80 have therefore become much more meaningful recently.
The content of the refresh register R is sent out on the lower half of
the address bus along with a refresh control signal while the CPU is
decoding and executing the fetched instruction. During refresh the
contents of the
Interrupt register I are sent out on the upper half of
the address bus.
Zilog introduced a number of peripheral parts for the Z80, which all
supported the Z80's interrupt handling system and I/O address space.
These included the Counter/Timer Channel (CTC), the SIO (Serial
Input Output), the DMA (Direct Memory Access), the PIO (Parallel
Input-Output) and the DART (Dual Asynchronous Receiver Transmitter).
As the product line developed, low-power, high-speed and
of these chips were produced.
Like the 8080, 8085 and
8086 processors, but unlike processors such as
Motorola 6800 and MOS Technology 6502, the Z80 and
8080 had a
separate control line and address space for I/O instructions. While
some Z80-based computers such as the
Osborne 1 used "Motorola-style"
memory mapped input/output devices, usually the I/O space was used to
address one of the many
Zilog peripheral chips compatible with the
Zilog I/O chips supported the Z80's new mode 2 interrupts which
simplified interrupt handling for large numbers of peripherals.
The Z80 was officially described as supporting 16-bit (64 KB)
memory addressing, and
8-bit (256 ports) I/O-addressing. All I/O
instructions actually assert the entire 16-bit address bus. OUT
(C),reg and IN reg,(C) places the contents of the entire 16 bit BC
register on the address bus; OUT (n),A and IN A,(n) places the
contents of the A register on b8-b15 of the address bus and n on b0-b7
of the address bus. A designer could choose to decode the entire 16
bit address bus on I/O operations in order to take advantage of this
feature, or use the high half of the address bus to select subfeatures
of the I/O device. This feature has also been used to minimise
decoding hardware requirements, such as in the
Amstrad CPC/PCW and
Second sources and derivatives
Mostek's Z80: MK3880
NEC's μPD780C Z80 second-sourced by NEC
Sharp's LH0080 Sharp version of the Z80
The T34BM1, a Russian Z80 clone
Toshiba TMPZ84C015; a standard Z80 with several Z80-family peripherals
on chip in a
The Z80 compatible
Z180 in a PLCC package
The Z80 compatible R800 in QFP
Z280 in a PLCC package
Mostek, who produced the first Z80 for Zilog, offered it as
second-source as MK3880.
SGS-Thomson (now STMicroelectronics) was a
second-source, too, with their Z8400. Sharp and
NEC developed second
sources for the NMOS Z80, the LH0080 and µPD780C respectively. The
µPD780C was used in the Sinclair
ZX80 and ZX81, original versions of
the ZX Spectrum, and several
MSX computers, and in musical
synthesizers such as
Oberheim OB-8 and others. The LH0080 was used in
various home computers and personal computers made by Sharp and other
Japanese manufacturers, including Sony
MSX computers, and a number of
computers in the
Sharp MZ series.
Toshiba made a CMOS-version, the TMPZ84C00, which is believed[by
whom?] (but not verified) to be the same design also used by
CMOS Z84C00. There were also Z80-chips made by
LG) and the BU18400 series of Z80-clones (including DMA, PIO, CTC,
DART and SIO) in NMOS and
CMOS made by ROHM Electronics.
In East Germany, an unlicensed clone of the Z80, known as the U880,
was manufactured. It was very popular and was used in Robotron's and
VEB Mikroelektronik Mühlhausen's computer systems (such as the
KC85-series) and also in many self-made computer systems. In Romania
another unlicensed clone could be found, named
MMN80CPU and produced
by Microelectronica, used in home computers like TIM-S, HC, COBRA.
Also, several clones of Z80 were created in the Soviet Union, notable
ones being the T34BM1, also called
КР1858ВМ1 (parallelling the
Russian 8080-clone KR580VM80A). The first marking was used in
pre-production series, while the second had to be used for a larger
production. Though, due to the collapse of Soviet microelectronics in
the late 1980s, there are many more T34BM1s than
Compatible with the original Z80
Hitachi developed the HD64180, a microcoded and partially dynamic Z80
in CMOS, with on chip peripherals and a simple MMU giving a 1 MB
address space. It was later second sourced by Zilog, initially as the
Z64180, and then in the form of the slightly modified Z180 which
has bus protocol and timings better adapted to Z80 peripheral chips.
Z180 has been maintained and further developed under Zilog's name, the
newest versions being based on the fully static S180/L180 core with
very low power draw and EMI (noise).
Toshiba developed the 84 pin Z84013 / Z84C13 and the 100 pin Z84015 /
Z84C15 series of "intelligent peripheral controllers", basically
ordinary NMOS and
CMOS Z80 cores with Z80 peripherals, watch dog
timer, power on reset, and wait state generator on the same chip.
Manufactured by Sharp as well as Toshiba. These products are today
second sourced by Zilog.
The 32-bit Z80 compatible
Zilog Z380, introduced 1994, is used mainly
in telecom equipment.
Zilog's fully pipelined Z80 compatible eZ80 with an 8/16/24-bit
word length and a linear 16 MB address space was introduced in
2001. It exists in versions with on chip SRAM or flash memory, as well
as with integrated peripherals. One variant has on chip MAC (media
access controller), and available software include a TCP/IP stack. In
contrast with the Z800 and Z280, there are only a few added
instructions (primarily LEAs, PEAs, and variable-address 16/24-bit
loads), but instructions are instead executed between 2 and 11 times
as clock cycle efficient as on the original Z80 (with a mean value
around 3-5 times). It is currently specified for clock frequencies up
to 50 MHz.
Kawasaki developed the binary compatible KL5C8400 which is
approximately 1.2-1.3 times as clock cycle efficient as the original
Z80 and can be clocked at up to 33 MHz. Kawasaki also produces
the KL5C80A1x family, which has peripherals as well as a small RAM on
chip; it is approximately as clock cycle efficient as the eZ80 and can
be clocked at up to 10 MHz (2006).
NEC uPD9002 was an hybrid CPU compatible with both Z80 and x86
The Chinese Actions Semiconductor's audio processor family of chips
(ATJ2085 and others) contains a Z80-compatible MCU together with a
24-bit dedicated DSP processor. These chips are used in many MP3
and media player products.
The T80 (VHDL) and TV80 (Verilog) synthesizable soft cores are
available from OpenCores.org.
Toshiba TLCS 900 series of high volume (mostly OTP)
microcontrollers are based on the Z80; they share the same basic
BC,DE,HL,IX,IY register structure, and largely the same instructions,
but are not binary compatible, while the previous TLCS 90 is
78K series microcontrollers are based on the Z80; they share
the same basic BC,DE,HL register structure, and has similar (but
differently named) instructions; not binary compatible.
Rabbit Semiconductor's Rabbit 2000/3000/4000
microprocessors/microcontrollers are based on the HD64180/Z180
architecture, although they are not fully binary compatible.
No longer produced
ASCII Corporation R800 was a fast 16-bit processor used in MSX
TurboR computers; it was software, but not hardware compatible with
the Z80 (signal timing, pinout & function of pins differ from the
Zilog's NMOS Z800 and
Z280 were 16-bit Z80-implementations
HD64180 / Z180) with a 16 MB paged MMU address space;
they added many orthogonalizations and addressing modes to the Z80
instruction set. Minicomputer features — such as user and system
modes, multiprocessor support, on chip MMU, on chip instruction and
data cache and so on — were seen rather as more complexity than as
functionality and support for the (usually electronics-oriented)
embedded systems designer, it also made it very hard to predict
instruction execution times.
Certain arcade games such as Pang/
Buster Bros use an encrypted
"Kabuki" Z80 CPU manufactured by VLSI Technology, where the decryption
keys are stored in its internal battery-backed memory, to avoid piracy
and illegal bootleg games.
See also: list of home computers by category §
Zilog Z80 and
The Z80A was used as the CPU in a number of gaming consoles, such as
During the late 1970s and early 1980s, the Z80 was used in a great
number of fairly anonymous business-oriented machines with the CP/M
operating system, a combination that dominated the market at the
time. Four well-known examples of Z80 business computers
CP/M are the Heathkit H89, the portable Osborne 1, the Kaypro
series, and the Epson QX-10. Research Machines manufactured the 380Z
and 480Z microcomputers which were networked with a thin Ethernet type
LAN and CP/NET in 1981. Other manufacturers of such systems included
Xerox (820 range),
Sanyo (MBC-1000/1100/1200), 
Toshiba (T100) and a number of more obscure firms. Some systems
used multi-tasking operating system software (like MP/M) to share the
one processor between several concurrent users.
In the U.S., the
Radio Shack TRS-80, introduced in 1977, as well as
the Models II, III, 4, and the proposed Model V, used the Z80. A
TRS-80 clones were produced by companies like Lobo (Max-80),
LNW (LNW-80), and Hong Kong-based EACA (
Video Genie and derivatives
TRZ-80, PMC-80, and Dick Smith System 80). In the Netherlands a TRS-80
Model III clone was produced that had
CP/M capability; this was the
Aster CT-80. The
Coleco Adam hybrid computer/game console could use
Colecovision games as well as CP/M. In the United Kingdom, Sinclair
Research used the Z80 and Z80A in its ZX80, ZX81, and
ZX Spectrum home
computers. These were marketed in the USA by Timex as the
Amstrad used the Z80A in their
Amstrad CPC and
PCW ranges and an early UK computer, the
Nascom 1 and 2 also used it.
The Z80 powered a great many home computers adhering to the MSX
standard in Japan, Asia, and to a lesser extent, Europe and South
America (some 5 million in
Japan alone). Also in
Japan Sharp used the
Z80 in its MZ and X1 series. The Hong Kong-based
VTech made its Laser
200 home computer with a Z80. In Germany an Apple-
CP/M hybrid called
the Base 108 paired a Z80 with a 6502. Similarly the Commodore 128
featured a Z80 processor alongside its
MOS Technology 8502
MOS Technology 8502 processor
CP/M compatibility. Other 6502 architecture computers on the
market at the time, such as the BBC Micro, Apple II, and the 6510
based Commodore 64, could make use of the Z80 with an external
unit, a plug-in card, or an expansion ROM cartridge. The Microsoft
Z-80 SoftCard for the
Apple II was a particularly successful add-on
card and one of Microsoft's few hardware products of the era.
In 1981, Multitech (later to become Acer) introduced the
Microprofessor I, a simple and inexpensive training system for the Z80
microprocessor. Currently, it is still manufactured and sold by Flite
Electronics International Limited in Southampton, England.
Embedded systems and consumer electronics
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Z80-based PABX. The Z80 is third chip in from the left, to the right
of the chip with the hand-written white label on it.
Zilog Z80 has long been a popular microprocessor in embedded
systems and microcontroller cores, where it remains in widespread
use today. The following list provides examples of such
applications of the Z80, including uses in consumer electronics
IBM PC-XT's hard drive controller, which was actually an IBM
adaptation of the Xebec 1410 SASI controller, but on a
PC-XT bus, not
a SASI bus.
Office equipment such as matrix printers, fax machines, answering
machines, and photocopiers are known examples. The original
Deskjet printer used a Z180.
Industrial programmable logic controllers (PLCs) use the Z80 in CPU
modules, for auxiliary functions such as analog I/O, or in
It has also been employed in robots, for example for speech
recognition and low level tasks such as servo processors in pick
and place machines.
RS-232 multiplexers connecting large numbers of old style "terminals"
to minicomputers or mainframes used arrays of Z80 CPU/SIO boards.
Applications such as TV broadcast vision mixers have used the Z80 for
embedded real time subtasks.
It has also been used in Seagate Technology's and other manufacturers'
Credit card consoles controlling fuel pumps used Z80 CPU and PIOs (US
patents 4930665, 4962462 and 5602745).
Retail industry point-of-sale credit card terminals manufactured by
VeriFone used the Z80 processor.
Several PC expansion cards, such as Adaptecs
SCSI boards, have been
using the Z80/
Z180 and peripheral chips.
Z380 have been used in telecommunication equipment such as
telephone switches and various kinds of modems.
Stofor message switch, used extensively by banks and brokers in
the UK was Z80 based.
Cash registers and store management systems
Home automation, wireless sprinkler control and wireless mesh using
the N8VEM open source homebrew system.
Breathalyzer equipment used by law enforcement agencies.
Amstrad NC100/NC200 and
Cambridge Z88 notebook computers made in
the United Kingdom used the Z80.
Amstrad in the UK produced an early PDA called the PenPad, or PDA600,
which was built around a 14 MHz Z180.
Z80 was often used in coin-operated arcade games, and was commonly
used as the main CPU, sound or video coprocessors.
games feature a single Z80 as the main CPU, and
Frogger used two
Galaxian and arcade games such as King & Balloon and
Check Man that use the
Galaxian boardset also use a Z80 as the
main CPU. Other
Namco licensed arcade games such as
other games that use the
Galaga boardset such as Bosconian, Dig
Dug, Xevious, and Super
Xevious use three Z80 microprocessors running
in parallel for the main CPU, graphics, and sound. Later Sega
System 16, 18, X, and Y;
Capcom CPS1 and CPS2; SNK Neo Geo MVS use
68000 and Z80 combination as co processors or sound CPUs.
It was also found in home video game consoles such as the
Sega Master System and
Sega Game Gear video game
consoles, as an audio and general-purpose co-processor in the Sega
Genesis and as an audio controller and co-processor to the Motorola
68000 in the SNK Neo-Geo.
Game Boy and
Game Boy Color handheld game systems used an
8080-derived processor with some Z80 instructions added (CB prefix) as
well as unique auto-increment/decrement addressing modes. The CPU was
Sharp Corporation LR35902 running at 4.19 MHz in the
original and Pocket models, and 8.39 MHz in the Color model. This
processor was later included in the
Game Boy Advance / SP / Micro
taking up a new role as a co-processor for backwards compatibility
Game Boy / Color games (except Micro) and to add legacy 8-bit
sounds to supplement the digital samples in
Game Boy Advance games.
Various scientific and graphing calculators use the Z80, including the
Texas Instruments TI-73, TI-81, TI-82, TI-83, TI-83+, TI-84+, TI-85
Sharp produced a series of pocket computers based on custom processors
that were Z80 compatible. Examples include PC-1500, PC-1600 and
The Ericsson GA628 mobile phone uses the Z80 CPU.
In Russia, Z80 and its clones were widely used in multi-functional
land line phones with Caller ID.
S1 MP3 player
S1 MP3 player type digital audio players use the Z80
MIDI sequencers such as
Polyphonic Keyboard and Sequencer,
Zyklus MPS, and Roland MSQ700 were built around the Z80.[citation
MIDI controllers and switches such as Waldorf Midi-Bay MB-15 and
Several polyphonic analog synthesizers used it for keyboard-scanning
(also wheels, knobs, displays...) and
D/A or PWM control of analog
levels; in newer designs, sometimes sequencing or MIDI-communication.
The Z80 was also often involved in the sound generation itself,
implementing LFOs, envelope generators and so on. Known examples
Sequential Circuits Prophet 5, Prophet 10, Prophet T8, Prophet
600, Six-Trak, Multitrak, MAX, and Split-8
MemoryMoog six-voice synthesizer
Oberheim OB-8 eight-voice synthesizer with MIDI
Roland Jupiter-8 eight-voice synthesizer
VEM Tiracon 6V six-voice analog synthesizer (1987) with
U880 CPU from
East Germany (Deutsche Demokratische Republik)
Digital sampling synthesizers such as the Emulator I, Emulator II, and
Akai S700 12-bit Sampler, as well as drum machines like the E-mu
E-mu Drumulator, and the Sequential Circuits
Drumtraks, used Z80 processors.
Many Lexicon reverberators (PCM70, LXP15, LXP1, MPX100) used one or
more Z80s for user interface and LFO generation where dedicated
hardware provided DSP functions.
The ADA MP-1 and Digitech GSP 2101/2112/2120,
MIDI controlled, vacuum
tube, guitar pre-amplifiers.
List of home computers by category
Small Device C Compiler
The Digital Group
^ Only in CMOS, National made no NMOS version, according to Oral
History with Federico Faggin
Federico Faggin oral history.
^ These were named the Z80 CTC (counter/timer), Z80 DMA (direct memory
access), Z80 DART (dual asynchronous receiver-transmitter), Z80 SIO
(synchronous communication controller), and Z80 PIO (parallel
^ a b c d Balch, Mark (2003-06-18). "Digital Fundamentals". Complete
Digital Design: A Comprehensive Guide to Digital Electronics and
Computer System Architecture. Professional Engineering. New York, New
McGraw-Hill Professional. p. 122.
^ a b The Seybold report on professional computing. Seybold
Publications. 1983. In the
8-bit world, the two most popular
microcomputers are the Z80 and 6502 computer chips.
Zilog included several "traps" in the layout of the chip to try to
delay this copying. According to Faggin, an
NEC engineer later told
him it had cost them several months of work, before they were able to
get their μPD780 to function.
^ Anderson 1994, p. 51
Zilog manufactured the Z80 as well as most of their other products
for many years until they sold their manufacturing plants and become
the "fabless" company they are today.
^ Anderson 1994, p. 57
^ a b Brock, Gerald W. (2003). The second information revolution.
Harvard University Press. ISBN 978-0-674-01178-6.
^ "History of the 8-bit: travelling far in a short time". InfoWorld.
Vol. 4 no. 47. Palo Alto, CA: Popular Computing Inc.
November 29, 1982. pp. 58–60. ISSN 0199-6649.
^ Shima, Masatoshi; Federico Faggin; Ralph Ungermann (August 19,
1976). "Z-80 chip set heralds third microprocessor generation".
Electronics. New York. 49 (17): 32–33 McGraw–Hill.
^ See Federico Faggin, oral history.
^ Mathur. Introduction to Microprocessors. p. 111.
ISBN 978-0-07-460222-5. The register architecture of the Z80 is
more innovative than that of the 8085
^ Ciarcia 1981, pp. 31,32
^ Although the
8080 had 16-bit addition and 16-bit increment and
decrement instructions, it had no explicit 16-bit subtraction, and no
overflow flag. The Z80 complemented this with the ADC HL,rr and SBC
HL,rr instructions which sets the new overflow flag accordingly. (The
8080 compatible ADD HL,rr does not.)
^ a b Wai-Kai Chen (2002). The circuits and filters handbook. CRC
Press. p. 1943. ISBN 978-0-8493-0912-0. interrupt processing
commences according to the interrupt method stipulated by the IM i,
i=0, 1, or 2, instruction. If i=1, for direct method, the PC is loaded
with 0038H. If i=0, for vectored method, the interrupting device has
the opportunity to place the op-code for one byte . If i=2, for
indirect vector method, the interrupting device must then place a byte
. The Z80 then uses this byte where one of 128 interrupt vectors can
be selected by the byte .
^ Notably to simultaneously handle the 32-bit mantissas of two
operands in the 40-bit floating point format used in the Sinclair home
computers. They were also used in a similar fashion in some earlier
but lesser known Z80 based computers, such as the Swedish
ABC 80 and
^ As this refresh does not need to transfer any data, just output
sequential row-adresses, it occupies less than 1.5 T-states. The
dedicated M1-signal (machine cycle one) in the Z80 can be used to
allow memory chips the same amount of access time for instruction
fetches as for data access, i.e almost two full T-states out of the 4T
fetch cycle (as well as out of the 3T data read cycle). The Z80 could
use memory with the same range of access times as the
8080 (or the
8086) at the same clock frequency. This long M1-signal (relative to
the clock) also meant that the Z80 could employ about 4-5 times the
internal frequency of a 6800, 6502 or similar using the same type of
^ Adrian, Andre. "Z80, the
8-bit Number Cruncher".
^ Popular Computing. McGraw-Hill. 1983. p. 15.
^ Markoff, John (18 October 1982). "Zilog's speedy Z80 soups up 8-bit
to 16-bit perfofrmance". InfoWorld.
InfoWorld Media Group. p. 1.
^ Unlike the original nMOS version, which used dynamic latches and
could not be stopped for more than a few thousand clock cycles.
^ Electronic design. Hayden. 1988. p. 142. In addition to
supporting the entire Z80 instruction set, the Z180
^ Ganssle, Jack G. (1992). "The Z80 Lives!". The designers picked an
architecture compatible with the Z80, giving Z80 users a completely
software compatible upgrade path. The 64180 processor runs every Z80
instruction exactly as a Z80 does
^ This variable HL pointer was actually the only way to access memory
(for data) in the Datapoint 2200, and hence also in the
Intel 8008. No
direct addresses could be used to access data.
^ Kilobaud. 1001001. 1977. p. 22.
^ Zaks, Rodnay (1982). Programming the Z80 (3rd ed.). SYBEX.
p. 62. ISBN 978-0-89588-069-7.
^ See Z80 oral history.
^ a b c Steve Heath. (2003).
Embedded systems design. Oxford: Newnes.
p. 21. ISBN 978-0-7506-5546-0.
^ "Z80 Flag Affection". www.z80.info. Thomas Scherrer. Retrieved June
^ It is not actually possible to encode this instruction on the Intel
8086 or later processors. See
Intel reference manuals.
^ Frank Durda IV. "8080/Z80 Instruction Set".
^ "8080A/ 8-Bit N-Channel Microprocessor".
Intel Component Data
Catalog 1978. Santa Clara, CA:
Intel Corporation. 1978.
pp. 11–17. All mnemonics copyright
Intel Corporation 1977
^ Jump (JP) instructions, which load the program counter with a new
instruction address, do not themselves access memory. Absolute and
relative forms of the jump reflect this by omitting the round brackets
from their operands. Register based jump instructions such as "JP
(HL)" include round brackets in an apparent deviation from this
convention."Z80 Relocating Macro Assembler User's Guide" (PDF).
^ Scanlon, Leo J. (1988). 8086/8088/80286 assembly language. Brady
Books. p. 12. ISBN 978-0-13-246919-7. The
software-compatible with the
8080 at the assembly-language
^ Nelson, Ross P. (1988). The 80386 book: assembly language
programmer's guide for the 80386.
Microsoft Press. p. 2.
ISBN 978-1-55615-138-5. An
Intel translator program could convert
8080 assembler programs into
8086 assembler programs
^ a b "Z80 CPU Introduction". Zilog. 1995. It has a language of 252
root instructions and with the reserved 4 bytes as prefixes, accesses
an additional 308 instructions.
^ Sanchez, Julio; Canton, Maria P. (2008). Software Solutions for
Engineers And Scientists. Taylor & Francis. p. 65.
ISBN 978-1-4200-4302-0. The
8-bit microprocessors that preceded
the 80x86 family (such as the
Intel 8080, the
Zilog Z80, and the
Motorola) did not include multiplication.
^ The Z80 redefines the P (parity) flag of the
8080 as P/V
(parity/overflow), and arithmetic instructions on the Z80 set it to
indicate overflow rather than parity. Also, bit 1 of the F (flags)
register, unused on the 8080, is defined on the Z80 as N, a flag that
indicates whether the last arithmetic instruction executed was a
subtraction or addition, and the Z80 DAA instruction checks the N flag
and behaves differently in the latter case, so a subtraction followed
later by DAA will yield a different result on a Z80 than on an 8080.
^ "8080/Z80 Instruction Sets". Quick and Dirty
8080 Assembler. Frank
Durda. Retrieved July 25, 2016.
^ Froehlich, Robert A. (1984). The free software catalog and
directory. Crown Publishers. p. 133. ISBN 978-0-517-55448-7.
Undocumented Z80 codes allow 8 bit operations with IX and IY
^ a b Bot, Jacco J. T. "Z80 Undocumented Instructions". Home of the
Z80 CPU. If an opcode works with the registers HL, H or L then if that
opcode is preceded by #DD (or #FD) it works on IX, IXH or IXL (or IY,
IYH, IYL), with some exceptions. The exceptions are instructions like
LD H,IXH and LD L,IYH
^ Robin Nixon The
Amstrad Notepad Advanced User Guide ,Robin Nixon,
1993 ISBN 1-85058-515-6, pages 219-223
Zilog (2005). Z80 Family CPU User Manual (PDF). Zilog.
^ Ciarcia 1981, p. 65
^ Zaks, Rodnay (1989). Programming the Z80. Sybex. p. 200.
ISBN 978-0-89588-069-7. ADD A, n Add accumulator with immediate
data n. MEMORY Timing: 2 M cycles; 7 T states.
^ Ciarcia 1981, p. 63
^ Ciarcia 1981, p. 77
^ Ciarcia 1981, p. 36
^ Ciarcia 1981, p. 58
^ "Z80 User Manual,
Special Registers pg. 3". www.zilog.com. Zilog.
Retrieved June 14, 2016.
^ "Z80 Family CPU Peripherals User Manual" (PDF). EEWORLD Datasheet.
ZiLOG. 2001. Retrieved April 30, 2014.
^ Young, Sean (1998). "Z80 Undocumented Features (in software
behaviour)". The I/O instructions use the whole of the address bus,
not just the lower 8 bits. So in fact, you can have 65536 I/O ports in
a Z80 system (the Spectrum uses this). IN r,(C), OUT (C),r and all the
I/O block instructions put the whole of BC on the address bus. IN
A,(n) and OUT (n),A put A*256+n on the address bus.
^ "Overview of the SHARP MZ-series". SharpMZ.org. Most MZ's use the
8bit CPU LH0080 / Z80 [...]
^ Ganssle, Jack G. (1992). "The Z80 Lives!". The 64180 is a
Hitachi-supplied Z80 core with numerous on-chip "extras". Zilog's
version is the Z180, which is essentially the same part.
^ Ganssle, Jack G. (1992). "The Z80 Lives!". Both
Toshiba and Zilog
sell the 84013 and 84015, which are Z80 cores with conventional Z80
peripherals integrated on-board.
EZ80 ACCLAIM Product Family". Zilog.
^ Electronic Business Asia. Cahners Asia Limited. 1997. p. 5.
Kawasaki's KL5C80A12, KL5C80A16 and KL5C8400 are high speed
and CPU. Their CPU code, KC80 is compatible with Zilog's Z80 at binary
level. KC80 executes instructions about four times faster than Z80 at
the same clock rate
^ "Hardware specs". S1mp3.org. 2005.
^ "Projects :: OpenCores".
^ "Section 6 MOS MPU, MCU, and Peripherals Market Trends" (PDF).
^ Axelson, Jan (2003). Embedded ethernet and internet complete.
Lakeview research. p. 93. ISBN 978-1-931448-00-0. Rabbit
Semiconductor's Rabbit 3000 microprocessor, which is a much improved
and enhanced derivative of ZiLOG, Inc.'s venerable Z80
^ Hyder, Kamal; Perrin, Bob (2004).
Embedded systems design using the
Rabbit 3000 microprocessor. Newnes. p. 32.
ISBN 978-0-7506-7872-8. The Rabbit parts are based closely on the
Z180 architecture, although they are not binary compatible with
^ Holtz, Herman (1985).
Computer work stations. Chapman and Hall.
p. 223. ISBN 978-0-412-00491-9. and
CP/M continued to
8-bit world of microcomputers.
^ Dvorak, John C. (10 May 1982). "After CP/M, object oriented
operating systems may lead the field". InfoWorld. Vol. 4
InfoWorld Media Group. p. 20. ISSN 0199-6649.
The idea of a generic operating system is still in its infancy. In
many ways it begins with
CP/M and the mishmash of early
8080 and Z80
Sanyo MBC-1000 small-business microcomputer". Google Books.
International Data Group. Retrieved April 4, 2018.
Sanyo MBC-1000". Old-computers dot com. New York Internet.
Retrieved April 4, 2018.
Toshiba T100". Oldcomputers dot net. Retrieved April 4, 2018.
^ Byte. McGraw-Hill. 1986. p. 274. C-128
CP/M uses both the Z80
and 8502 processors. The Z80 executes most of the
^ Petersen, Marty (6 February 1984). "Review: Premium Softcard IIe".
InfoWorld. Vol. 6 no. 6.
InfoWorld Media Group. p. 64.
Several manufacturers, however, make Z80 coprocessor boards that plug
into the Apple II.
^ Popular Computing. McGraw-Hill. 1986. p. 22. The Commodore 64
CP/M package contains a plug-in cartridge with a Z80 microprocessor
CP/M operating system on a disk.
^ Ian R. Sinclair. (2000). Practical electronics handbook. Oxford,
Angleterre: Newnes. p. 204. ISBN 978-0-7506-4585-0.
^ A. Meystel. (1991). Autonomous mobile robots : vehicles with
cognitive control. Teaneck, N.J.: World Scientific. p. 44.
^ American Society of Cinematographers (1983). American
cinematographer. ASC Holding. p. 18.
^ Bruce A. Artwick. (1980). Microcomputer interfacing. Englewood
Cliffs, N.J.: Prentice-Hall: Prentice-Hall. p. 25.
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dispensing system with electronically controlled valve remote from
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^ "Fuel dispenser electronics design". Hans B. Atchley, John J.
Ronchetti, Sr., Gilbarco Inc. 1995-01-18.
^ Anderson, Nate. "Source code requests force breathalyzer maker to
sober up". Ars Technica. The Intoxilyzer 5000EN, a breathalyzer, runs
on a pair of Z80 processors
^ "Game Board Schematic". Midway
Pac-Man Parts and Operating Manual
(PDF). Chicago, Illinois: Midway Games. December 1980. pp. 33,
34. Retrieved 2014-01-20.
^ "Game Logic Schematic". Midway
Galaxian Parts and Operating Manual
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24. Retrieved 2014-01-20.
^ "Schematics and Wiring Diagrams". Midway Galega Parts and Operating
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ColecoVision uses the Z80
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^ Reid, Gordon (March 1999). "
Sequential Circuits Prophet Synthesizers
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