Junction-Less nanowire transistor (JLNT) is a type of

Field-effect transistor The field-effect transistor (FET) is a type of transistor that uses an electric field to control the flow of current in a semiconductor. FETs (JFETs or MOSFETs) are devices with three terminals: ''source'', ''gate'', and ''drain''. FETs co ...

(FET) which channel is one or multiple nanowires and does not present any junction.

Existing devices

Multiple JLNT devices were manufactured in various labs:

Tyndall National Institute in Ireland

JLT is a nanowire-based

transistor upright=1.4, gate (G), body (B), source (S) and drain (D) terminals. The gate is separated from the body by an insulating layer (pink). A transistor is a semiconductor device used to Electronic amplifier, amplify or electronic switch, switch ...

that has no

gate A gate or gateway is a point of entry to or from a space enclosed by walls. The word derived from old Norse "gat" meaning road or path; But other terms include ''yett and port''. The concept originally referred to the gap or hole in the wall ...

junction. (Even

MOSFET The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is a type of field-effect transistor (FET), most commonly fabricated by the controlled oxidation of silicon. It has an insulated gate, the voltage of which d ...

has a gate junction, although its gate is electrically insulated from the controlled region.) Junctions are difficult to fabricate, and, because they are a significant source of current leakage, they waste significant power and heat. Eliminating them held the promise of cheaper and denser microchips. The JNT uses a simple nanowire of silicon surrounded by an electrically isolated "wedding ring" that acts to gate the flow of electrons through the wire. This method has been described as akin to squeezing a garden hose to gate the flow of water through the hose. The nanowire is heavily n-doped, making it an excellent conductor. Crucially the gate, comprising silicon, is heavily p-doped; and its presence depletes the underlying silicon nanowire thereby preventing carrier flow past the gate.

LAAS

A Junction-Less Vertical Nano-Wire FET (JLVNFET) manufacturing process was developed in Laboratory for Analysis and Architecture of Systems (LAAS).

Electrical Behaviour

Thus the device is turned off not by reverse bias voltage applied to the gate, as in the case of conventional

but by full depletion of the channel. This depletion is caused due to work-function difference ( Contact_potentials) between the gate material and doped silicon in the nanowire. The JNT uses bulk conduction instead of surface channel conduction. The current drive is controlled by doping concentration and not by gate capacitance. Germanium has been used instead of silicon nanowires.

References

Junctionless Nanowire Transistor: Properties and Device GuidelinesFerain Junctionless Transistors (pdf)
Transistor types Nanoelectronics {{Electronics-stub