The AMD Bobcat Family 14h is a

microarchitecture In computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as µarch or uarch, is the way a given instruction set architecture (ISA) is implemented in a particular processor. A given ISA may be imp ...

created by AMD for its AMD APUs, aimed at a low-power/low-cost market. It was revealed during a speech from AMD executive vice-president Henri Richard in

Computex COMPUTEX Taipei, or Taipei International Information Technology Show (), is a computer expo held annually in Taipei, Taiwan. Since the early 2000s, it is one of the largest computer and technology trade shows in the world. The last COMPUTEX was ...

2007 and was put into production Q1 2011. One of the major supporters was executive vice-president

Mario A. Rivas is a character created by Japanese video game designer Shigeru Miyamoto. He is the title character of the ''Mario'' franchise and the mascot of Japanese video game company Nintendo. Mario has appeared in over 200 video games since his crea ...

who felt it was difficult to compete in the x86 market with a single core optimized for the 10–100 W range and actively promoted the development of the simpler core with a target range of 1–10 W. In addition, it was believed that the core could migrate into the hand-held space if the power consumption can be reduced to less than 1 W. ''Bobcat'' cores are used together with GPU cores in

accelerated processing unit AMD Accelerated Processing Unit (APU), formerly known as Fusion, is a series of 64-bit microprocessors from Advanced Micro Devices (AMD), combining a general-purpose AMD64 central processing unit (CPU) and integrated graphics processing unit ...

s (APUs) under the "'' Fusion''" brand. A simplified architecture diagram was released at AMD's Analyst Day in November 2009. This is similar in concept with earlier AMD research in 2003,AMD 2003 Microprocessor Forum Slides
Slide 11
an
Slide 22
/ref> detailing the specifications and advantages of extending x86 "everywhere".

Design

The ''Bobcat'' x86 CPU core design has since been completed and implemented in AMD APU processor products with a TDP of 18 W or less. The core is targeted at low-power markets like netbooks/nettops, ultra-portable laptops, consumer electronics and the embedded market. Since its launch, Bobcat-based CPUs have also been used by OEMs on larger laptops. Architecture specifics: * 64-bit core *

Out-of-order execution In computer engineering, out-of-order execution (or more formally dynamic execution) is a paradigm used in most high-performance central processing units to make use of instruction cycles that would otherwise be wasted. In this paradigm, a proces ...

* Advanced

branch predictor In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch (e.g., an if–then–else structure) will go before this is known definitively. The purpose of the branch predictor is to improve the flow ...

* Dual x86 instruction decoder * 64-bit integer unit with two ALUs *

Floating-point unit In computing, floating-point arithmetic (FP) is arithmetic that represents real numbers approximately, using an integer with a fixed precision, called the significand, scaled by an integer exponent of a fixed base. For example, 12.345 can be ...

with two 64-bit pipes * Single channel 64-bit memory controller * 32 KiB instruction + 32 KiB data L1 cache * 512 KiB - 1 MiB L2 cache *

MMX MMX may refer to: * 2010, in Roman numerals Science and technology * MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel * MMX Mineração, a Brazilian mining company * Martian Moons eXploration, a Japane ...

, SSE,

SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier SSE i ...

SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...

SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitectu ...

, SSE4A, ABM In February 2013, AMD detailed plans for a successor to ''Bobcat'' codenamed ''

Jaguar The jaguar (''Panthera onca'') is a large cat species and the only living member of the genus ''Panthera'' native to the Americas. With a body length of up to and a weight of up to , it is the largest cat species in the Americas and the th ...

''.

Features

APU features table

Processors

In January 2011 AMD introduced several processors that have implemented the ''Bobcat'' core. This core is in the following AMD Accelerated Processors: AMD CMC60

^ E-Series & C-Series are standard parts, G-Series are embedded parts

References

External links

Dailytech report

RegHardware report

Bobcat presentation (video)
at ISSCC 2011
AMD Home Page
{{DEFAULTSORT:Bobcat AMD x86 microprocessors AMD microarchitectures X86 microarchitectures

Design

Features

Processors

See also

References

External links