A control register is a processor register
which changes or controls the general behavior of a CPU
or other digital device. Common tasks performed by control registers include interrupt
control, switching the addressing mode
control, and coprocessor
Control registers in x86
The CR0 register is 32 bits long on the 386
and higher processors. On x64
processors in long mode
, it (and the other control registers) is 64 bits long. CR0 has various control flags that modify the basic operation of the processor.
Reserved, the CPU will throw a #UD
exception when trying to access it.
Contains a value called Page Fault Linear Address (PFLA). When a page fault occurs, the address the program attempted to access is stored in the CR2 register.
thumb|Typical use of CR3 in address translation with 4 KiB
Used when virtual addressing
is enabled, hence when the PG bit is set in CR0. CR3 enables the processor to translate linear addresses into physical addresses by locating the page directory and page table
s for the current task. Typically, the upper 20 bits of CR3 become the ''page directory base register'' (PDBR), which stores the physical address of the first page directory entry. If the PCIDE bit in CR4
is set, the lowest 12 bits are used for the process-context identifier
Used in protected mode to control operations such as virtual-8086 support, enabling I/O breakpoints, page size extension
and machine-check exceptions
Reserved, same case as CR1.
Additional Control registers in x86-64
Extended Feature Enable Register (EFER) is a model-specific register
added in the AMD K6
processor, to allow enabling the SYSCALL
/SYSRET instruction, and later for entering and exiting long mode
. This register becomes architectural in AMD64
and has been adopted by Intel
as IA32_EFER. Its MSR number is 0xC0000080.
CR8 is a new register accessible in 64-bit mode using the REX prefix. CR8 is used to prioritize external interrupts
and is referred to as the task-priority register (TPR).
architecture allows software to define up to 15 external interrupt-priority classes. Priority classes are numbered from 1 to 15, with priority-class 1 being the lowest and priority-class 15 the highest. CR8 uses the four low-order bits for specifying a task priority
and the remaining 60 bits are reserved and must be written with zeros.
System software can use the TPR register to temporarily block low-priority interrupts from interrupting a high-priority task. This is accomplished by loading TPR with a value corresponding to the highest-priority interrupt that is to be blocked. For example, loading TPR with a value of 9 (1001b) blocks all interrupts with a priority class of 9 or less, while allowing all interrupts with a priority class of 10 or more to be recognized. Loading TPR with 0 enables all external interrupts. Loading TPR with 15 (1111b) disables all external interrupts.
The TPR is cleared to 0 on reset.
XCR0 and XSS
XCR0, or Extended Control Register 0, is a control register which is used to toggle the storing or loading of registers related to specific CPU features using the XSAVE/XRSTOR instructions. It is also used with some features to enable or disable the processor's ability to execute their corresponding instructions. It can be accessed using the privileged XSETBV and nonprivileged XGETBV instructions.
There is also the IA32_XSS MSR, which is located at address 0DA0h. The IA32_XSS MSR controls bits of XCR0 which are considered to be "supervisor" state, and should be invisible to regular programs. It operates with the privileged XSAVES and XRSTORS instructions by adding supervisor state to the data they operate with. Put simply, if the X87 state was enabled in XCR0 and PT state was enabled in IA32_XSS, the XSAVE instruction would only store X87 state, while the privileged XSAVES would store both X87 and PT states. Because it is an MSR, it can be accessed using the RDMSR and WRMSR instructions.
* General-purpose register
* Test register
* Model-specific register
* Debug register
* Flag byte
* Status register
Intel 64 and IA-32 Architectures Developer's Manual: Vol. 3AIntel 64 and IA-32 Architectures Software Developer ManualsTech Docs: AMD64Wyatt's World: Cracking Open the Pentium III
Category:Operating system technology
Category:Central processing unit