The program status word (PSW) is a register that performs the function of a
status register
A status register, flag register, or condition code register (CCR) is a collection of status flag bits for a processor. Examples of such registers include FLAGS register in the x86 architecture, flags in the program status word (PSW) register in ...
and
program counter
The program counter (PC), commonly called the instruction pointer (IP) in Intel x86 and Itanium microprocessors, and sometimes called the instruction address register (IAR), the instruction counter, or just part of the instruction sequencer, i ...
, and sometimes more. The term is also applied to a copy of the PSW in storage. This article only discusses the PSW in the
IBM System/360
The IBM System/360 (S/360) is a family of mainframe computer systems that was announced by IBM on April 7, 1964, and delivered between 1965 and 1978. It was the first family of computers designed to cover both commercial and scientific applic ...
and its successors, and follows the IBM convention of numbering bits starting with 0 as the leftmost (most significant) bit.
Although certain fields within the PSW may be tested or set by using non-privileged instructions, testing or setting the remaining fields may only be accomplished by using privileged instructions.
Contained within the PSW are the two bit
condition code, representing zero, positive, negative, overflow, and similar flags of other architectures'
status register
A status register, flag register, or condition code register (CCR) is a collection of status flag bits for a processor. Examples of such registers include FLAGS register in the x86 architecture, flags in the program status word (PSW) register in ...
s.
Conditional branch instructions test this encoded as a four bit value, with each bit representing a test of one of the four condition code values, 2
3 + 2
2 + 2
1 + 2
0. (Since IBM uses big-endian bit numbering, mask value 8 selects code 0, mask value 4 selects code 1, mask value 2 selects code 2, and mask value 1 selects code 3.)
The 64-bit PSW describes (among other things)
*
Interrupt masks
* Privilege states
* Condition code
* Instruction address
In the early instances of the architecture (System/360 and early System/370), the instruction address was 24 bits; in later instances (XA/370), the instruction address was 31 bits plus a mode bit (24 bit addressing mode if zero; 31 bit addressing mode if one) for a total of 32 bits.
In the present instances of the architecture (
z/Architecture
z/Architecture, initially and briefly called ESA Modal Extensions (ESAME), is IBM's 64-bit complex instruction set computer (CISC) instruction set architecture, implemented by its mainframe computers. IBM introduced its first z/Architect ...
), the instruction address is 64 bits and the PSW itself is 128 bits.
The PSW may be loaded by the LOAD PSW instruction (
LPSW or LPSWE). Its contents may be examined with the Extract PSW instruction (EPSW).
Format
S/360
On all but
360/20, the PSW has the following formats. S/360 Extended PSW format only applies to the
360/67 with bit 8 of control register 6 set.
S/370
S/370 Extended Architecture (S/370-XA)
Enterprise Systems Architecture (ESA)
z/Architecture
Notes
References
;S360
:
;func67
:
;S370
:
;S370-XA
:
;S370-ESA
:
;z
:
{{DEFAULTSORT:Status Register
Control flow
Central processing unit
Digital registers
IBM System/360 mainframe line