Verilog-AMS is a derivative of the
Verilog
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is als ...
hardware description language
In computer engineering, a hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, and most commonly, digital logic circuits.
A hardware description language e ...
that includes analog and mixed-signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems. It extends the event-based simulator loops of Verilog/SystemVerilog/VHDL, by a continuous-time simulator, which solves the differential equations in analog-domain. Both domains are coupled: analog events can trigger digital actions and vice versa.
Overview
The Verilog-AMS standard was created with the intent of enabling designers of analog and mixed signal systems and integrated circuits to create and use modules that encapsulate high-level behavioral descriptions as well as structural descriptions of systems and components.
Verilog-AMS is an industry standard modeling language for mixed signal circuits. It provides both continuous-time and event-driven modeling semantics, and so is suitable for analog, digital, and mixed analog/digital circuits. It is particularly well suited for verification of very complex analog, mixed-signal and RF integrated circuits.
Verification of Complex Analog Integrated Circuits
Verilog and Verilog/AMS are not procedural programming languages, but event-based hardware description language
In computer engineering, a hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, and most commonly, digital logic circuits.
A hardware description language e ...
s (HDLs). As such, they provide sophisticated and powerful language features for definition and synchronization of parallel actions and events. On the other hand, many actions defined in HDL program statements can run in parallel (somewhat similar to threads and tasklets in procedural languages, but much more fine-grained). However, Verilog/AMS can be coupled with procedural languages like the ANSI C language using the Verilog Procedural Interface
The Verilog Procedural Interface (VPI), originally known as PLI 2.0, is an interface primarily intended for the C programming language. It allows behavioral Verilog code to invoke C functions, and C functions to invoke standard Verilog system task ...
of the simulator, which eases testsuite implementation, and allows interaction with legacy code or testbench equipment.
The original intention of the Verilog-AMS committee was a single language for both analog and digital design, however due to delays in the merger process it remains at Accellera
Accellera Systems Initiative (Accellera) is a standards organization that supports a mix of user and vendor standards and open interfaces development in the area of electronic design automation (EDA) and integrated circuit (IC) design and manufactu ...
while Verilog
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is als ...
evolved into SystemVerilog and went to the IEEE.
Code example
Verilog/AMS is a superset of the Verilog digital HDL, so all statements in digital domain work as in Verilog
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is als ...
(see there for examples). All analog parts work as in Verilog-A
Verilog-A is an industry standard modeling language for analog circuits. It is the continuous-time subset of Verilog-AMS. A few commercial applications may export MEMS designs in Verilog-A format.
History
Verilog-A was created out of a need to st ...
.
The following code example in Verilog-AMS shows a DAC which is an example for analog processing which is triggered by a digital signal:
`include "constants.vams"
`include "disciplines.vams"
// Simple DAC model
module dac_simple(aout, clk, din, vref);
// Parameters
parameter integer bits = 4 from :24
parameter integer td = 1n from :inf); // Processing delay of the DAC
// Define input/output
input clk, vref;
input [bits-1:0din;
output aout;
//Define port types
logic clk;
logic [bits-1:0] din;
electrical aout, vref;
// Internal variables
real aout_new, ref;
integer i;
// Change signal in the analog part
analog begin
@(posedge clk) begin // Change output only for rising clock edge
aout_new = 0;
ref = V(vref);
for(i=0; i
end
end
V(aout) <+ transition(aout_new, td, 5n); // Get a smoother transition when output level changes
end
endmodule
The ADC
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model is reading analog signals in the digital blocks:
`include "constants.vams"
`include "disciplines.vams"
// Simple ADC model
module adc_simple(clk, dout, vref, vin);
// Parameters
parameter integer bits = 4 from :24 // Number of bits
parameter integer td = 1 from :inf); // Processing delay of the ADC
// Define input/output
input clk, vin, vref;
output [bits-1:0dout;
//Define port types
electrical vref, vin;
logic clk;
reg [bits-1:0] dout;
// Internal variables
real ref, sample;
integer i;
initial begin
dout = 0;
end
// Perform sampling in the digital blocks for rising clock edge
always @(posedge clk) begin
sample = V(vin);
ref = V(vref);
for(i=0; i ref) begin
dout <= #(td) 1;
sample = sample - ref;
end
else
dout <= #(td) 0;
end
end
endmodule
See also
* VHDL-AMS
VHDL-AMS is a derivative of the hardware description language VHDL (IEEE standard 1076-1993). It includes analog and mixed-signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems (IEEE 1076.1-1999).
The VHDL-AMS ...
References
External links
* I. Miller and T. Cassagnes, "Verilog-AMS Eases Mixed Mode Signal Simulation," ''Technical Proceedings of the 2000 International Conference on Modeling and Simulation of Microsystems'', pp. 305–308, Available: https://web.archive.org/web/20070927051749/http://www.nsti.org/publ/MSM2000/T31.01.pdf
General
Accellera Verilog Analog Mixed-Signal Group
verilogams.com
— User's manual for Verilog-AMS and Verilog-A
The Designer's Guide Community, Verilog-A/MS
— Examples of models written in Verilog-AMS
EDA.ORG AMS Wiki
- Issues, future development, SystemVerilog integration
Open Source Implementations
OpenVAMS, an Open-Source VerilogAMS-1.3 Parser with internal VPI-like representation
V2000 project - Verilog-AMS parser & elaborator
{{Programmable Logic
Hardware description languages