![NVIDIA T20 and T30 chips](https://upload.wikimedia.org/wikipedia/commons/3/36/NVIDIA_T20_and_T30_chips.jpg)
Tegra is a
system on a chip (SoC) series developed by
Nvidia
Nvidia CorporationOfficially written as NVIDIA and stylized in its logo as VIDIA with the lowercase "n" the same height as the uppercase "VIDIA"; formerly stylized as VIDIA with a large italicized lowercase "n" on products from the mid 1990s to ...
for mobile devices such as
smartphone
A smartphone is a portable computer device that combines mobile telephone and computing functions into one unit. They are distinguished from feature phones by their stronger hardware capabilities and extensive mobile operating systems, whic ...
s,
personal digital assistant
A personal digital assistant (PDA), also known as a handheld PC, is a variety mobile device which functions as a personal information manager. PDAs have been mostly displaced by the widespread adoption of highly capable smartphones, in part ...
s, and
mobile Internet devices. The Tegra integrates an
ARM architecture central processing unit
A central processing unit (CPU), also called a central processor, main processor or just Processor (computing), processor, is the electronic circuitry that executes Instruction (computing), instructions comprising a computer program. The CPU per ...
(CPU),
graphics processing unit
A graphics processing unit (GPU) is a specialized electronic circuit designed to manipulate and alter memory to accelerate the creation of images in a frame buffer intended for output to a display device. GPUs are used in embedded systems, m ...
(GPU),
northbridge,
southbridge, and
memory controller
The memory controller is a digital circuit that manages the flow of data going to and from the computer's main memory. A memory controller can be a separate chip or integrated into another chip, such as being placed on the same die or as an int ...
onto one package. Early Tegra SoCs are designed as efficient multimedia processors. The Tegra-line evolved to emphasize performance for gaming and machine learning applications without sacrificing power efficiency, before taking a drastic shift in direction towards platforms that provide
vehicular automation
Vehicular automation involves the use of mechatronics, artificial intelligence, and multi-agent systems to assist the operator of a vehicle (car, aircraft, watercraft, or otherwise).Hu, J.; Bhowmick, P.; Lanzon, A.,Group Coordinated Control ...
with the applied "Drive" brand name on reference boards and its semiconductors; and with the "Jetson" brand name for boards adequate for AI applications within e.g. robots or drones, and for various smart high level automation purposes.
History
The Tegra APX 2500 was announced on February 12, 2008. The Tegra 6xx product line was revealed on June 2, 2008, and the APX 2600 was announced in February 2009. The APX chips were designed for smartphones, while the Tegra 600 and 650 chips were intended for
smartbook
A smartbook was a class of mobile device that combined certain features of both a smartphone and netbook computer, produced between 2009 and 2010.
Smartbooks were advertised with features such as always on, all-day battery life, 3G, or Wi-Fi conn ...
s and
mobile Internet devices (MID).
The first product to use the Tegra was
Microsoft
Microsoft Corporation is an American multinational technology corporation producing computer software, consumer electronics, personal computers, and related services headquartered at the Microsoft Redmond campus located in Redmond, Washin ...
's
Zune HD
The Zune HD is a portable media player in the Zune product family released on September 15, 2009, by Microsoft. It was a direct competitor with Apple's iPod Touch series of mobile devices. It was initially released in 16 and 32 GB capacities. A ...
media player in September 2009, followed by the
Samsung
The Samsung Group (or simply Samsung) ( ko, 삼성 ) is a South Korean multinational manufacturing conglomerate headquartered in Samsung Town, Seoul, South Korea. It comprises numerous affiliated businesses, most of them united under the ...
M1. Microsoft's
Kin __NOTOC__
Kin usually refers to kinship and family.
Kin or KIN may also refer to:
Culture and religion
*Otherkin, people who identify as not entirely human
*Kinism, a white supremacist religious movement
* Kinh, the majority ethnic group of V ...
was the first cellular phone to use the Tegra; however, the phone did not have an app store, so the Tegra's power did not provide much advantage. In September 2008, Nvidia and
Opera Software
Opera is a Norwegian multinational technology company and subsidiary of Kunlun that specializes in web browser development, fintech, as well as services such as Opera News and YoYo Games. The company's total user base, including users of its ...
announced that they would produce a version of the
Opera 9.5
The history of the Opera (web browser), Opera web browser began in 1994 when it was started as a research project at Telenor, the largest Norwegian telecommunications company. In 1995, the project branched out into a separate company named Opera ...
browser optimized for the Tegra on
Windows Mobile
Windows Mobile is a discontinued family of mobile operating systems developed by Microsoft for smartphones and personal digital assistants.
Its origin dated back to Windows CE in 1996, though Windows Mobile itself first appeared in 2000 as Pock ...
and
Windows CE
Windows Embedded Compact, formerly Windows Embedded CE, Windows Powered and Windows CE, is an operating system subfamily developed by Microsoft as part of its Windows Embedded family of products.
Unlike Windows Embedded Standard, which is base ...
. At
Mobile World Congress 2009, Nvidia introduced its port of
Google
Google LLC () is an American Multinational corporation, multinational technology company focusing on Search Engine, search engine technology, online advertising, cloud computing, software, computer software, quantum computing, e-commerce, ar ...
's
Android to the Tegra.
On January 7, 2010, Nvidia officially announced and demonstrated its next generation Tegra system-on-a-chip, the Nvidia Tegra 250, at
Consumer Electronics Show 2010. Nvidia primarily supports Android on Tegra 2, but booting other ARM-supporting operating systems is possible on devices where the
bootloader
A bootloader, also spelled as boot loader or called boot manager and bootstrap loader, is a computer program that is responsible for booting a computer.
When a computer is turned off, its softwareincluding operating systems, application code, an ...
is accessible. Tegra 2 support for the
Ubuntu
Ubuntu ( ) is a Linux distribution based on Debian and composed mostly of free and open-source software. Ubuntu is officially released in three editions: '' Desktop'', ''Server'', and ''Core'' for Internet of things devices and robots. All ...
Linux distribution was also announced on the Nvidia developer forum.
Nvidia announced the first
quad-core
A multi-core processor is a microprocessor on a single integrated circuit with two or more separate processing units, called cores, each of which reads and executes program instructions. The instructions are ordinary CPU instructions (such a ...
SoC at the February 2011
Mobile World Congress event in Barcelona. Though the chip was codenamed Kal-El, it is now branded as Tegra 3. Early benchmark results show impressive gains over Tegra 2, and the chip was used in many of the tablets released in the second half of 2011.
In January 2012,
Nvidia
Nvidia CorporationOfficially written as NVIDIA and stylized in its logo as VIDIA with the lowercase "n" the same height as the uppercase "VIDIA"; formerly stylized as VIDIA with a large italicized lowercase "n" on products from the mid 1990s to ...
announced that
Audi
Audi AG () is a German automotive manufacturer of luxury vehicles headquartered in Ingolstadt, Bavaria, Germany. As a subsidiary of its parent company, the Volkswagen Group, Audi produces vehicles in nine production facilities worldwide.
Th ...
had selected the Tegra 3 processor for its
In-Vehicle Infotainment
In-car entertainment (ICE), or in-vehicle infotainment (IVI), is a collection of hardware and software in automobiles that provides audio or video entertainment. In car entertainment originated with car audio systems that consisted of radios and c ...
systems and digital instruments display. The processor will be integrated into
Audi
Audi AG () is a German automotive manufacturer of luxury vehicles headquartered in Ingolstadt, Bavaria, Germany. As a subsidiary of its parent company, the Volkswagen Group, Audi produces vehicles in nine production facilities worldwide.
Th ...
's entire line of vehicles worldwide, beginning in 2013. The process is
ISO 26262
ISO 26262, titled "Road vehicles – Functional safety", is an international standard for functional safety of electrical and/or electronic systems that are installed in serial production road vehicles (excluding mopeds), defined by the Interna ...
-certified.
In summer of 2012
Tesla Motors
Tesla, Inc. ( or ) is an American multinational automotive and clean energy company headquartered in Austin, Texas. Tesla designs and manufactures electric vehicles (electric cars and trucks), battery energy storage from home to grid- ...
began shipping the
Model S
The Tesla Model S is a battery-powered liftback car serving as the flagship model of Tesla, Inc. The Model S features a dual-motor, all-wheel drive layout, although earlier versions of the Model S featured a rear-motor and rear-wheel drive l ...
all electric, high performance
sedan, which contains two NVIDIA Tegra 3D Visual Computing Modules (VCM). One VCM powers the 17-inch
touchscreen
A touchscreen or touch screen is the assembly of both an input ('touch panel') and output ('display') device. The touch panel is normally layered on the top of an electronic visual display of an information processing system. The display is ofte ...
infotainment system, and one drives the 12.3-inch all
digital instrument cluster
In an automobile, an electronic instrument cluster, digital instrument panel or ''digital dash'' for short, is a set of instrumentation, including the speedometer, that is displayed with a digital readout rather than with the traditional anal ...
."
In March 2015, Nvidia announced the Tegra X1, the first SoC to have a graphics performance of 1 teraflop. At the announcement event, Nvidia showed off
Epic Games' Unreal Engine
Unreal Engine (UE) is a 3D computer graphics game engine developed by Epic Games, first showcased in the 1998 first-person shooter game '' Unreal''. Initially developed for PC first-person shooters, it has since been used in a variety of g ...
4 "Elemental" demo, running on a Tegra X1.
On October 20, 2016, Nvidia announced that the
Nintendo Switch hybrid video game console will be powered by Tegra hardware. On March 15, 2017, TechInsights revealed the Nintendo Switch is powered by a custom Tegra X1 (model T210), with lower clockspeeds.
Specifications
Tegra APX
; Tegra APX 2500:
* Processor:
ARM11
ARM11 is a group of 32-bit RISC ARM processor cores licensed by ARM Holdings. The ARM11 core family consists of ARM1136J(F)-S, ARM1156T2(F)-S, ARM1176JZ(F)-S, and ARM11MPCore. Since ARM11 cores were released from 2002 to 2005, they are no lon ...
600 MHz MPCore (originally GeForce ULV)
** Suffix: APX (formerly CSX)
* Memory: NOR or NAND flash, Mobile DDR
* Graphics: Image processor (
FWVGA
The graphics display resolution is the width and height dimension of an electronic visual display device, measured in pixels. This information is used for electronic devices such as a computer monitor. Certain combinations of width and height ...
854×480 pixels)
** Up to 12
megapixel
In digital imaging, a pixel (abbreviated px), pel, or picture element is the smallest addressable element in a raster image, or the smallest point in an all points addressable display device.
In most digital display devices, pixels are the sm ...
s camera support
** LCD controller supports resolutions up to 1280×1024
* Storage: IDE for SSD
* Video codecs: up to
720p
720p (1280×720 px; also called HD ready, standard HD or just HD) is a progressive HDTV signal format with 720 horizontal lines/1280 columns and an aspect ratio (AR) of 16:9, normally known as widescreen HDTV (1.78:1). All major HDTV broadcast ...
MPEG-4 AVC/H.264 and
VC-1
SMPTE 421, informally known as VC-1, is a video coding format. Most of it was initially developed as Microsoft's proprietary video format Windows Media Video 9 in 2003. With some enhancements including the development of a new Advanced Profile, ...
decoding
* Includes
GeForce
GeForce is a brand of graphics processing units (GPUs) designed by Nvidia. As of the GeForce 40 series, there have been eighteen iterations of the design. The first GeForce products were discrete GPUs designed for add-on graphics boards, inte ...
ULV support for
OpenGL ES
OpenGL for Embedded Systems (OpenGL ES or GLES) is a subset of the OpenGL computer graphics rendering application programming interface (API) for rendering 2D and 3D computer graphics such as those used by video games, typically hardware-accele ...
2.0,
Direct3D Mobile, and programmable shaders
* Output:
HDMI
High-Definition Multimedia Interface (HDMI) is a proprietary audio/video interface for transmitting uncompressed video data and compressed or uncompressed digital audio data from an HDMI-compliant source device, such as a display controlle ...
,
VGA
Video Graphics Array (VGA) is a video display controller and accompanying de facto graphics standard, first introduced with the IBM PS/2 line of computers in 1987, which became ubiquitous in the PC industry within three years. The term can no ...
,
composite video,
S-Video
S-Video (also known as separate video, Y/C, and erroneously Super-Video ) is an analog video signal format that carries standard-definition video, typically at 525 lines or 625 lines. It encodes video luma and chrominance on two separate chan ...
, stereo jack, USB
*
USB On-The-Go
USB On-The-Go (USB OTG or just OTG) is a specification first used in late 2001 that allows USB devices, such as tablets or smartphones, to act as a host, allowing other USB devices, such as USB flash drives, digital cameras, mouse or keybo ...
; Tegra APX 2600:
* Enhanced NAND flash
* Video codecs:
** 720p H.264 Baseline Profile encode or decode
** 720p VC-1/WMV9 Advanced Profile decode
**
D-1 D1, D01, D.I, D.1 or D-1 can refer to:
Science and technology Biochemistry and medicine
* ATC code D01 ''Antifungals for dermatological use'', a subgroup of the Anatomical Therapeutic Chemical Classification System
* Dopamine receptor D1, Dopamine ...
MPEG-4 Simple Profile encode or decode
Tegra 6xx
; Tegra 600:
* Targeted for GPS segment and automotive
* Processor: ARM11 700 MHz MPCore
* Memory:
low-power DDR (
DDR-333, 166 MHz)
* SXGA, HDMI, USB, stereo jack
* HD camera 720p
; Tegra 650:
* Targeted for GTX of handheld and notebook
* Processor: ARM11 800 MHz MPCore
*
Low power DDR (
DDR-400, 200 MHz)
* Less than 1 watt envelope
* HD image processing for advanced digital still camera and HD camcorder functions
* Display supports
1080p
1080p (1920×1080 progressively displayed pixels; also known as Full HD or FHD, and BT.709) is a set of HDTV high-definition video modes characterized by 1,920 pixels displayed across the screen horizontally and 1,080 pixels down the screen ve ...
at 24 frame/s, HDMI v1.3, WSXGA+ LCD and CRT, and NTSC/PAL TV output
* Direct support for Wi-Fi, disk drives, keyboard, mouse, and other peripherals
* A complete
board support package
In embedded systems, a board support package (BSP) is the layer of software containing hardware-specific boot firmware and device drivers and other routines that allow a given embedded operating system, for example a real-time operating system ( ...
(BSP) to enable fast time to market for Windows Mobile-based designs
Tegra 2
![Motorola Xoom - nvidia Tegra 2 T20-H-A2 on main board-0121](https://upload.wikimedia.org/wikipedia/commons/a/af/Motorola_Xoom_-_nvidia_Tegra_2_T20-H-A2_on_main_board-0121.jpg)
The second generation Tegra SoC has a
dual-core
A multi-core processor is a microprocessor on a single integrated circuit with two or more separate processing units, called cores, each of which reads and executes program instructions. The instructions are ordinary CPU instructions (such ...
ARM Cortex-A9 CPU, an ultra low power (ULP) GeForce GPU, a 32-bit memory controller with either LPDDR2-600 or DDR2-667 memory, a 32KB/32KB L1 cache per core and a shared 1MB L2 cache. Tegra 2's Cortex A9 implementation does not include ARM's SIMD extension,
NEON. There is a version of the Tegra 2 SoC supporting 3D displays; this SoC uses a higher clocked CPU and GPU.
The Tegra 2 video decoder is largely unchanged from the original Tegra and has limited support for HD formats. The lack of support for high-profile H.264 is particularly troublesome when using online video streaming services.
Common features:
* CPU cache: L1: 32 KB instruction + 32 KB data, L2: 1 MB
*
40 nm
4 (four) is a number, numeral and digit. It is the natural number following 3 and preceding 5. It is the smallest semiprime and composite number, and is considered unlucky in many East Asian cultures.
In mathematics
Four is the smalle ...
semiconductor technology
1 Pixel shader
In computer graphics, a shader is a computer program that calculates the appropriate levels of light, darkness, and color during the Rendering (computer graphics), rendering of a 3D scene - a process known as ''shading''. Shaders have evolved ...
s :
Vertex shader
In computer graphics, a shader is a computer program that calculates the appropriate levels of light, darkness, and color during the rendering of a 3D scene - a process known as ''shading''. Shaders have evolved to perform a variety of speci ...
s :
Texture mapping unit
In computer graphics, a texture mapping unit (TMU) is a component in modern graphics processing units (GPUs). They are able to rotate, resize, and distort a bitmap image to be placed onto an arbitrary plane of a given 3D model as a texture, in a ...
s :
Render output unit
In computer graphics, the render output unit (ROP) or raster operations pipeline is a hardware component in modern graphics processing units (GPUs) and one of the final steps in the rendering process of modern graphics cards. The pixel pipeline ...
s
Devices
Tegra 3
![OUYA-Console-set-h](https://upload.wikimedia.org/wikipedia/commons/a/af/OUYA-Console-set-h.jpg)
NVIDIA's Tegra 3 (
codename
A code name, call sign or cryptonym is a code word or name used, sometimes clandestinely, to refer to another name, word, project, or person. Code names are often used for military purposes, or in espionage. They may also be used in industrial c ...
d "
Kal-El
Superman is a superhero who appears in American comic books published by DC Comics. The character was created by writer Jerry Siegel and artist Joe Shuster, and debuted in the comic book ''Action Comics'' #1 (cover-dated June 1938 and publish ...
") is functionally a SoC with a quad-core
ARM Cortex-A9 MPCore
The ARM Cortex-A9 MPCore is a 32-bit multi-core processor that provides up to 4 cache-coherent cores, each implementing the ARM v7 architecture instruction set. It was introduced in 2007.
Features
Key features of the Cortex-A9 core are:
* ...
CPU, but includes a fifth "companion" core in what Nvidia refers to as a "variable
SMP architecture". While all cores are Cortex-A9s, the companion core is manufactured with a low-power silicon process. This core operates transparently to applications and is used to reduce power consumption when processing load is minimal. The main quad-core portion of the CPU powers off in these situations.
Tegra 3 is the first Tegra release to support ARM's SIMD extension,
NEON.
The GPU in Tegra 3 is an evolution of the Tegra 2 GPU, with 4 additional pixel shader units and higher clock frequency. It can also output video up to 2560×1600 resolution and supports
1080p
1080p (1920×1080 progressively displayed pixels; also known as Full HD or FHD, and BT.709) is a set of HDTV high-definition video modes characterized by 1,920 pixels displayed across the screen horizontally and 1,080 pixels down the screen ve ...
MPEG-4 AVC/h.264 40 Mbit/s High-Profile, VC1-AP, and simpler forms of MPEG-4 such as DivX and Xvid.
The Tegra 3 was released on November 9, 2011.
Common features:
* CPU cache: L1: 32 KB instruction + 32 KB data, L2: 1 MB
*
40 nm
4 (four) is a number, numeral and digit. It is the natural number following 3 and preceding 5. It is the smallest semiprime and composite number, and is considered unlucky in many East Asian cultures.
In mathematics
Four is the smalle ...
LPG semiconductor technology by
TSMC
Taiwan Semiconductor Manufacturing Company Limited (TSMC; also called Taiwan Semiconductor) is a Taiwanese multinational semiconductor contract manufacturing and design company. It is the world's most valuable semiconductor company, the world' ...
1 Pixel shader
In computer graphics, a shader is a computer program that calculates the appropriate levels of light, darkness, and color during the Rendering (computer graphics), rendering of a 3D scene - a process known as ''shading''. Shaders have evolved ...
s :
Vertex shader
In computer graphics, a shader is a computer program that calculates the appropriate levels of light, darkness, and color during the rendering of a 3D scene - a process known as ''shading''. Shaders have evolved to perform a variety of speci ...
s :
Texture mapping unit
In computer graphics, a texture mapping unit (TMU) is a component in modern graphics processing units (GPUs). They are able to rotate, resize, and distort a bitmap image to be placed onto an arbitrary plane of a given 3D model as a texture, in a ...
s :
Render output unit
In computer graphics, the render output unit (ROP) or raster operations pipeline is a hardware component in modern graphics processing units (GPUs) and one of the final steps in the rendering process of modern graphics cards. The pixel pipeline ...
s
Devices
Tegra 4
The Tegra 4 (
codename
A code name, call sign or cryptonym is a code word or name used, sometimes clandestinely, to refer to another name, word, project, or person. Code names are often used for military purposes, or in espionage. They may also be used in industrial c ...
d "
Wayne") was announced on January 6, 2013 and is a SoC with a quad-core CPU, but includes a fifth low-power Cortex A15 companion core which is invisible to the OS and performs background tasks to save power. This power-saving configuration is referred to as "variable SMP architecture" and operates like the similar configuration in Tegra 3.
The GeForce GPU in Tegra 4 is again an evolution of its predecessors. However, numerous feature additions and efficiency improvements were implemented. The number of processing resources was dramatically increased, and clock rate increased as well. In 3D tests, the Tegra 4 GPU is typically several times faster than that of Tegra 3. Additionally, the Tegra 4 video processor has full support for hardware decoding and encoding of
WebM
WebM is an audiovisual media file format. It is primarily intended to offer a royalty-free alternative to use in the HTML5 video and the HTML5 audio elements. It has a sister project, WebP, for images. The development of the format is sponsored ...
video (up to 1080p 60Mbit/s @ 60fps).
Along with Tegra 4, Nvidia also introduced i500, an optional
software
Software is a set of computer programs and associated software documentation, documentation and data (computing), data. This is in contrast to Computer hardware, hardware, from which the system is built and which actually performs the work.
...
modem based on Nvidia's acquisition of
Icera
Icera Inc. is a British multinational fabless semiconductor company headquartered in Bristol, United Kingdom, and a wholly owned subsidiary of Nvidia Corporation. It has developed soft modem chipsets for the mobile devices market, including mo ...
, which can be reprogrammed to support new network standards. It supports category 3 (100Mbit/s) LTE but will later be updated to Category 4 (150Mbit/s).
Common features:
* CPU cache: L1: 32 KB instruction + 32 KB data, L2: 2 MB
*
28 nm
8 (eight) is the natural number following 7 and preceding 9.
In mathematics
8 is:
* a composite number, its proper divisors being , , and . It is twice 4 or four times 2.
* a power of two, being 2 (two cubed), and is the first number of the ...
HPL semiconductor technology
1 Pixel shader
In computer graphics, a shader is a computer program that calculates the appropriate levels of light, darkness, and color during the Rendering (computer graphics), rendering of a 3D scene - a process known as ''shading''. Shaders have evolved ...
s :
Vertex shader
In computer graphics, a shader is a computer program that calculates the appropriate levels of light, darkness, and color during the rendering of a 3D scene - a process known as ''shading''. Shaders have evolved to perform a variety of speci ...
s :
Pixel pipelines (pairs 1x TMU and 1x ROP)
Devices
Tegra 4i
The Tegra 4i (
codename
A code name, call sign or cryptonym is a code word or name used, sometimes clandestinely, to refer to another name, word, project, or person. Code names are often used for military purposes, or in espionage. They may also be used in industrial c ...
d "
Grey
Grey (more common in British English) or gray (more common in American English) is an intermediate color between black and white. It is a neutral or achromatic color, meaning literally that it is "without color", because it can be composed o ...
") was announced on February 19, 2013. With hardware support for the same audio and video formats,
but using Cortex-A9 cores instead of Cortex-A15, the Tegra 4i is a low-power variant of the Tegra 4 and is designed for phones and tablets. Unlike its Tegra 4 counterpart, the Tegra 4i also integrates the
Icera
Icera Inc. is a British multinational fabless semiconductor company headquartered in Bristol, United Kingdom, and a wholly owned subsidiary of Nvidia Corporation. It has developed soft modem chipsets for the mobile devices market, including mo ...
i500
LTE/
HSPA+ baseband processor
A baseband processor (also known as baseband radio processor, BP, or BBP) is a device (a chip or part of a chip) in a network interface controller that manages all the radio functions (all functions that require an antenna); however, this term i ...
onto the same die.
Common features:
*
28 nm
8 (eight) is the natural number following 7 and preceding 9.
In mathematics
8 is:
* a composite number, its proper divisors being , , and . It is twice 4 or four times 2.
* a power of two, being 2 (two cubed), and is the first number of the ...
HPM semiconductor technology
* CPU cache: L1: 32 KB instruction + 32 KB data, L2: 1 MB
1 Pixel shader
In computer graphics, a shader is a computer program that calculates the appropriate levels of light, darkness, and color during the Rendering (computer graphics), rendering of a 3D scene - a process known as ''shading''. Shaders have evolved ...
s :
Vertex shader
In computer graphics, a shader is a computer program that calculates the appropriate levels of light, darkness, and color during the rendering of a 3D scene - a process known as ''shading''. Shaders have evolved to perform a variety of speci ...
s :
Pixel pipelines (pairs 1x TMU and 1x ROP)
= Devices
=
Tegra K1
Nvidia
Nvidia CorporationOfficially written as NVIDIA and stylized in its logo as VIDIA with the lowercase "n" the same height as the uppercase "VIDIA"; formerly stylized as VIDIA with a large italicized lowercase "n" on products from the mid 1990s to ...
's Tegra K1 (codenamed "
Logan") features ARM Cortex-A15 cores in a 4+1 configuration similar to Tegra 4, or Nvidia's
64-bit
In computer architecture, 64-bit integers, memory addresses, or other data units are those that are 64 bits wide. Also, 64-bit CPUs and ALUs are those that are based on processor registers, address buses, or data buses of that size. A compu ...
Project Denver
Project Denver is the codename of a central processing unit designed by Nvidia that implements the ARMv8-A 64/ 32-bit instruction sets using a combination of simple hardware decoder and software-based binary translation (dynamic recompilation) ...
dual-core processor as well as a
Kepler
Johannes Kepler (; ; 27 December 1571 – 15 November 1630) was a German astronomer, mathematician, astrologer, natural philosopher and writer on music. He is a key figure in the 17th-century Scientific Revolution, best known for his laws o ...
graphics processing unit with support for Direct3D 12, OpenGL ES 3.1, CUDA 6.5,
OpenGL 4.4/
OpenGL 4.5, and
Vulkan
Vulkan is a low- overhead, cross-platform API, open standard for 3D graphics and computing. Vulkan targets high-performance real-time 3D graphics applications, such as video games and interactive media. Vulkan is intended to offer higher perfor ...
. Nvidia claims that it outperforms both the Xbox 360 and the PS3, whilst consuming significantly less power.
Support
Adaptive Scalable Texture Compression.
In late April 2014, Nvidia shipped the "Jetson TK1" development board containing a Tegra K1 SoC and running
Ubuntu Linux
Ubuntu ( ) is a Linux distribution based on Debian and composed mostly of free and open-source software. Ubuntu is officially released in three editions: '' Desktop'', ''Server'', and ''Core'' for Internet of things devices and robots. Al ...
.
* Processor:
**
32-bit variant quad-core
ARM Cortex-A15 MPCore R3 + low power companion core
** or 64-bit variant with dual-core
Project Denver
Project Denver is the codename of a central processing unit designed by Nvidia that implements the ARMv8-A 64/ 32-bit instruction sets using a combination of simple hardware decoder and software-based binary translation (dynamic recompilation) ...
(variant once codenamed "
Stark")
* GPU consisting of 192 ALUs using
Kepler
Johannes Kepler (; ; 27 December 1571 – 15 November 1630) was a German astronomer, mathematician, astrologer, natural philosopher and writer on music. He is a key figure in the 17th-century Scientific Revolution, best known for his laws o ...
technology
*
28 nm
8 (eight) is the natural number following 7 and preceding 9.
In mathematics
8 is:
* a composite number, its proper divisors being , , and . It is twice 4 or four times 2.
* a power of two, being 2 (two cubed), and is the first number of the ...
HPM process
* Released in Q2 2014
* Power consumption: 8 watts
1 Unified Shaders :
Texture mapping unit
In computer graphics, a texture mapping unit (TMU) is a component in modern graphics processing units (GPUs). They are able to rotate, resize, and distort a bitmap image to be placed onto an arbitrary plane of a given 3D model as a texture, in a ...
s :
Render output unit
In computer graphics, the render output unit (ROP) or raster operations pipeline is a hardware component in modern graphics processing units (GPUs) and one of the final steps in the rendering process of modern graphics cards. The pixel pipeline ...
s
2 ARM Large Physical Page Extension (LPAE) supports 1
TiB (2
40 bytes). The 8
GiB
The byte is a unit of digital information that most commonly consists of eight bits. Historically, the byte was the number of bits used to encode a single character of text in a computer and for this reason it is the smallest addressable unit ...
limitation is part-specific.
Devices
In December 2015, the web page of wccftech.com published an article stating that Tesla is going to use a Tegra K1 based design derived from the template of the Nvidia Visual Computing Module (VCM) for driving the infotainment systems and providing visual driving aid in the respective vehicle models of that time. This news has, as of now, found no similar successor or other clear confirmation later on in any other place on such a combination of a multimedia with an auto pilot system for these vehicle models.
Tegra X1
![Nintendo-Switch-wJoyCons-BlRd-Standing-FL](https://upload.wikimedia.org/wikipedia/commons/8/88/Nintendo-Switch-wJoyCons-BlRd-Standing-FL.jpg)
Released in 2015, Nvidia's Tegra X1 (codenamed "Erista") features two cpu clusters, one with four
ARM Cortex-A57
The ARM Cortex-A57 is a central processing unit implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings. The Cortex-A57 is an out-of-order superscalar pipeline. It is available as SIP core to licensees, and its design makes it ...
cores and the other with four
ARM Cortex-A53
The ARM Cortex-A53 is one of the first two central processing units implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings' Cambridge design centre. The Cortex-A53 is a 2-wide decode superscalar processor, capable of dual- ...
cores, as well as a
Maxwell-based graphics processing unit.
It supports
Adaptive Scalable Texture Compression.
Only one cluster of cores can be active at once, with the cluster switch being handled by software on the BPMP-L. Devices utilizing the Tegra X1 have only been seen to utilize the cluster with the more powerful ARM Cortex-A57 cores. The other cluster with four ARM Cortex-A53 cores cannot be accessed without first powering down the Cortex-A57 cores (both clusers must be in the CC6 off state). Nvidia has removed the ARM Cortex-A53 cores from later versions of technical documentation, implying that they have been removed from the die. The Tegra X1 was found to be vulnerable to a Fault Injection (FI) voltage glitching attack, which allowed for arbitrary code execution and homebrew software on the devices it was implemented in.
A revision (codenamed "Mariko") with greater power efficiency, known officially as Tegra X1+ was released in 2019,
fixing the Fusée Gelée exploit. It's also known as T214 and T210B01.
*
CPU: ARMv8
ARM Cortex-A57
The ARM Cortex-A57 is a central processing unit implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings. The Cortex-A57 is an out-of-order superscalar pipeline. It is available as SIP core to licensees, and its design makes it ...
quad-core (64-bit) + (unused?)
ARM Cortex-A53
The ARM Cortex-A53 is one of the first two central processing units implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings' Cambridge design centre. The Cortex-A53 is a 2-wide decode superscalar processor, capable of dual- ...
quad-core (64-bit)
*
GPU
A graphics processing unit (GPU) is a specialized electronic circuit designed to manipulate and alter memory to accelerate the creation of images in a frame buffer intended for output to a display device. GPUs are used in embedded systems, mobi ...
:
Maxwell-based 256 core GPU (Jetson Nano: only 128 cores)
*
MPEG-4 HEVC
High Efficiency Video Coding (HEVC), also known as H.265 and MPEG-H Part 2, is a video compression standard designed as part of the MPEG-H project as a successor to the widely used Advanced Video Coding (AVC, H.264, or MPEG-4 Part 10). In compar ...
VP8
VP8 is an open and royalty-free video compression format released by On2 Technologies in 2008.
Initially released as a proprietary successor to On2's previous VP7 format, VP8 was released as an open and royalty-free format in May 2010 after Goo ...
encoding/decoding &
VP9
VP9 is an open and royalty-free video coding format developed by Google.
VP9 is the successor to VP8 and competes mainly with MPEG's High Efficiency Video Coding (HEVC/H.265).
At first, VP9 was mainly used on Google's video platform YouTube. ...
decoding support
(Jetson Nano: encoders are
H.265
H is the eighth letter of the Latin alphabet.
H may also refer to:
Musical symbols
* H number, Harry Halbreich reference mechanism for music by Honegger and Martinů
* H, B (musical note)
* H, B major
People
* H. (noble) (died after 12 ...
, H.264/Stereo,
VP8
VP8 is an open and royalty-free video compression format released by On2 Technologies in 2008.
Initially released as a proprietary successor to On2's previous VP7 format, VP8 was released as an open and royalty-free format in May 2010 after Goo ...
,
JPEG; decoders are
H.265
H is the eighth letter of the Latin alphabet.
H may also refer to:
Musical symbols
* H number, Harry Halbreich reference mechanism for music by Honegger and Martinů
* H, B (musical note)
* H, B major
People
* H. (noble) (died after 12 ...
, H.264/Stereo,
VP8
VP8 is an open and royalty-free video compression format released by On2 Technologies in 2008.
Initially released as a proprietary successor to On2's previous VP7 format, VP8 was released as an open and royalty-free format in May 2010 after Goo ...
,
VP9
VP9 is an open and royalty-free video coding format developed by Google.
VP9 is the successor to VP8 and competes mainly with MPEG's High Efficiency Video Coding (HEVC/H.265).
At first, VP9 was mainly used on Google's video platform YouTube. ...
,
VC-1
SMPTE 421, informally known as VC-1, is a video coding format. Most of it was initially developed as Microsoft's proprietary video format Windows Media Video 9 in 2003. With some enhancements including the development of a new Advanced Profile, ...
,
MPEG-2,
JPEG)
*
TSMC
Taiwan Semiconductor Manufacturing Company Limited (TSMC; also called Taiwan Semiconductor) is a Taiwanese multinational semiconductor contract manufacturing and design company. It is the world's most valuable semiconductor company, the world' ...
20 nm process
The 22 nm node is the process step following 32 nm process, 32 nm in CMOS MOSFET semiconductor device fabrication. The typical half-pitch (i.e., half the distance between identical features in an array) for a memory cell using the process is arou ...
for the Tegra X1
*TSMC
16 nm process
The 14 nm process refers to the MOSFET technology node that is the successor to the 22nm (or 20nm) node. The 14nm was so named by the International Technology Roadmap for Semiconductors (ITRS). Until about 2011, the node following 22nm was expec ...
for the Tegra X1+.
*
TDP:
** T210: 15 W, with average power consumption less than 10 W
** Jetson Nano: 10 W (mode 0); mode 1: 5W (only 2 CPU cores @ 918 MHz, GPU @ 640 MHz)
1 CPU frequency may be clocked differently than the maximum validated by Nvidia at the OEM's discretion
2 Unified Shaders :
Texture mapping unit
In computer graphics, a texture mapping unit (TMU) is a component in modern graphics processing units (GPUs). They are able to rotate, resize, and distort a bitmap image to be placed onto an arbitrary plane of a given 3D model as a texture, in a ...
s :
Render output unit
In computer graphics, the render output unit (ROP) or raster operations pipeline is a hardware component in modern graphics processing units (GPUs) and one of the final steps in the rendering process of modern graphics cards. The pixel pipeline ...
s
3 Maximum validated amout of memory, implementation is board specific
4 Maximum validated memory bandwidth, implementation is board specific
Devices
Tegra X2
Nvidia's Tegra X2 (codenamed "
Parker") features Nvidia's own custom general-purpose ARMv8-compatible core Denver 2 as well as code-named Pascal graphics processing core with
GPGPU
General-purpose computing on graphics processing units (GPGPU, or less often GPGP) is the use of a graphics processing unit (GPU), which typically handles computation only for computer graphics, to perform computation in applications traditiona ...
support. The chips are made using
FinFET
A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal-oxide-semiconductor field-effect transistor) built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, ...
process technology using
TSMC
Taiwan Semiconductor Manufacturing Company Limited (TSMC; also called Taiwan Semiconductor) is a Taiwanese multinational semiconductor contract manufacturing and design company. It is the world's most valuable semiconductor company, the world' ...
's 16 nm FinFET+ manufacturing process.
* CPU: Nvidia Denver2 ARMv8 (64-bit) dual-core + ARMv8 ARM Cortex-A57 quad-core (64-bit)
* RAM: up to 8GB
LPDDR4
* GPU:
Pascal-based, 256
CUDA
CUDA (or Compute Unified Device Architecture) is a parallel computing platform and application programming interface (API) that allows software to use certain types of graphics processing units (GPUs) for general purpose processing, an approach ...
cores; type: GP10B
* TSMC 16 nm,
FinFET
A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal-oxide-semiconductor field-effect transistor) built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, ...
process
* TDP: 7.5–15 W
[NVIDIA Announces Jetson TX2: Parker Comes To NVIDIA's Embedded System Kit](_blank)
, March 7, 2017
1 Unified Shaders :
Texture mapping unit
In computer graphics, a texture mapping unit (TMU) is a component in modern graphics processing units (GPUs). They are able to rotate, resize, and distort a bitmap image to be placed onto an arbitrary plane of a given 3D model as a texture, in a ...
s :
Render output unit
In computer graphics, the render output unit (ROP) or raster operations pipeline is a hardware component in modern graphics processing units (GPUs) and one of the final steps in the rendering process of modern graphics cards. The pixel pipeline ...
s (SM count)
Devices
Xavier
The Xavier Tegra SoC, named after the comic book character
Professor X, was announced on 28 September 2016, and by March 2019, it had been released. It contains 7 billion transistors and 8 custom ARMv8 cores, a Volta GPU with 512 CUDA cores, an open sourced
TPU (Tensor Processing Unit) called DLA (Deep Learning Accelerator). It is able to encode and decode
8K Ultra HD (7680×4320). Users can configure operating modes at 10 W, 15 W, and 30 W TDP as needed and the die size is 350 mm
2.
Nvidia confirmed the fabrication process to be
12 nm
1 (one, unit, unity) is a number representing a single or the only entity. 1 is also a numerical digit and represents a single unit of counting or measurement. For example, a line segment of ''unit length'' is a line segment of length 1. I ...
FinFET at CES 2018.
* CPU: Nvidia custom Carmel ARMv8.2-A (64-bit), 8 cores 10-wide superscalar
* GPU:
Volta-based, 512
CUDA
CUDA (or Compute Unified Device Architecture) is a parallel computing platform and application programming interface (API) that allows software to use certain types of graphics processing units (GPUs) for general purpose processing, an approach ...
cores with 1.4 TFLOPS;
type: GV11B
* TSMC
12 nm
1 (one, unit, unity) is a number representing a single or the only entity. 1 is also a numerical digit and represents a single unit of counting or measurement. For example, a line segment of ''unit length'' is a line segment of length 1. I ...
,
FinFET
A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal-oxide-semiconductor field-effect transistor) built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, ...
process
* 20 TOPS DL and 160
SPECint
SPECint is a computer benchmark specification for CPU integer processing power. It is maintained by the Standard Performance Evaluation Corporation (SPEC). SPECint is the integer performance testing component of the SPEC test suite. The first SPEC ...
@ 20 W;
30 TOPS DL @ 30 W
(TOPS DL = Deep Learning Tera-Ops)
** 20 TOPS DL via the GPU based tensor cores
** 10 TOPS DL (INT8) via the DLA unit that shall achieve 5 TFLOPS (FP16)
* 1.6 TOPS in the PVA unit (Programmable Vision Accelerator, for StereoDisparity/OpticalFlow/ImageProcessing)
* 1.5 GPix/s in the ISP unit (Image Signal Processor, with native full-range HDR and tile processing support)
* Video processor for 1.2 GPix/s encoding and 1.8 GPix/s decode
including 8k video support
* MIPI-CSI-3 with 16 lanes
* 1 Gbit/s Ethernet
* 10 Gbit/s Ethernet
1 Unified Shaders :
Texture mapping unit
In computer graphics, a texture mapping unit (TMU) is a component in modern graphics processing units (GPUs). They are able to rotate, resize, and distort a bitmap image to be placed onto an arbitrary plane of a given 3D model as a texture, in a ...
s :
Render output unit
In computer graphics, the render output unit (ROP) or raster operations pipeline is a hardware component in modern graphics processing units (GPUs) and one of the final steps in the rendering process of modern graphics cards. The pixel pipeline ...
s (SM count, Tensor Cores)
Devices
On the Linux Kernel Mailing List, a Tegra194 based development board with type ID "P2972-0000" got reported: ''The board consists of the P2888 compute module and the P2822 baseboard.''
Orin
![NVIDIA Orin press - die - annotated](https://upload.wikimedia.org/wikipedia/commons/b/bf/NVIDIA_Orin_press_-_die_-_annotated.jpg)
Nvidia announced the next-gen SoC codename
Orin
ORiN (Open Robot/Resource interface for the Network) is a standard network interface for FA (factory automation) systems. The Japan Robot Association proposed ORiN in 2002, and the ORiN Forum develops and maintains the ORiN standard.
Background ...
on March 27, 2018 at GPU Technology Conference 2018. It contains 17 billion transistors and 12 Arm Hercules cores and is capable of 200 INT8 TOPs @ 65W.
The Drive AGX Orin board system family was announced on December 18, 2019 at
GTC China 2019. Nvidia has sent papers to the press documenting that the known (from Xavier series) clock and voltage scaling on the semiconductors and by pairing multiple such chips a wider range of application can be realized with the thus resulting board concepts. The vehicle company NIO got announced by Nvidia for receiving a 4 Orin chip based board design for use in their cars.
The so far published specifications for Orin are:
* CPU: 12×
Arm Cortex-A78
The ARM Cortex-A78 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Ltd.'s Austin centre, set to be distributed amongst high-end devices in 2020–2021.
Design
The ARM Cortex-A78 is the successor t ...
AE (Hercules) ARMv8.2-A (64-bit)
* GPU: Ampere-based, 2048
CUDA
CUDA (or Compute Unified Device Architecture) is a parallel computing platform and application programming interface (API) that allows software to use certain types of graphics processing units (GPUs) for general purpose processing, an approach ...
cores and 64 tensor cores; "with up to 131 Sparse TOPs of INT8 Tensor compute, and up to 5.32 FP32 TFLOPs of CUDA compute."
** 5.3 CUDA TFLOPs (FP32)
** 10.6 CUDA TFLOPs (FP16)
* Samsung
8 nm process
* 275 TOPS (INT8) DL
** 170 TOPS DL (INT8) via the GPU
** 105 TOPS DL (INT8) via the 2x
NVDLA 2.0 units (
DLA, Deep Learning Accelerator)
* 85 TOPS DL (FP16)
* 5 TOPS in the PVA v2.0 unit (Programmable Vision Accelerator for Feature Tracking)
* 1.85 GPix/s in the ISP unit (Image Signal Processor, with native full-range HDR and tile processing support)
* Video processor for ? GPix/s encoding and ? GPix/s decode
* 4× 10 Gbit/s Ethernet, 1× 1 Gbit/s Ethernet
Nvidia announced the latest member of the family, "Orin Nano" in September 2022 at the GPU Technology Conference 2022. The Orin product line now features SoC and SoM(System-On-Module) based on the core Orin design and scaled for different uses from 60W all the way down to 5W. While less is known about the exact SoC's that are being manufactured, Nvidia has publicly shared detailed technical specifications about the entire Jetson Orin SoM product line. These module specifications illustrate how Orin scales providing insight into future devices that contain an Orin derived SoC.
1 Shader Processors :
Ray tracing cores :
Tensor Cores (SM count, GPCs, TPCs)
Devices
Atlan (Cancelled)
![Nvidia-Atlan-die-with-structural-annotations-preliminary](https://upload.wikimedia.org/wikipedia/commons/b/be/Nvidia-Atlan-die-with-structural-annotations-preliminary.png)
Nvidia announced the next-gen SoC codename
Atlan on April 12, 2021 at GPU Technology Conference 2021. Nvidia announced the cancellation of Atlan and their next SoC will be Thor.
Functional units known so far are:
*
Grace
Grace may refer to:
Places United States
* Grace, Idaho, a city
* Grace (CTA station), Chicago Transit Authority's Howard Line, Illinois
* Little Goose Creek (Kentucky), location of Grace post office
* Grace, Carroll County, Missouri, an uninco ...
Next Generation CPU (Arm Cortex-A715AE?)
* Ampere Next Generation GPU
* Bluefield DPU (Data Processing Unit)
* other Accelerators
* Security Engine
* Functional Safety Island
* On-Chip-Memory
* External Memory Interface(s)
* High-Speed-IO Interfaces
Thor
Nvidia announced the next-gen SoC codename Thor on September 20, 2022 at GPU Technology Conference 2022, replacing the cancelled Atlan.
Devices
*
Nvidia DRIVE Thor
Models comparison
* VLIW
Very long instruction word (VLIW) refers to instruction set architectures designed to exploit instruction level parallelism (ILP). Whereas conventional central processing units (CPU, processor) mostly allow programs to specify instructions to exe ...
-based Vec4:
Pixel shader
In computer graphics, a shader is a computer program that calculates the appropriate levels of light, darkness, and color during the Rendering (computer graphics), rendering of a 3D scene - a process known as ''shading''. Shaders have evolved ...
s +
Vertex shader
In computer graphics, a shader is a computer program that calculates the appropriate levels of light, darkness, and color during the rendering of a 3D scene - a process known as ''shading''. Shaders have evolved to perform a variety of speci ...
s. Since Kepler, Unified shaders are used.
Software support
FreeBSD
FreeBSD supports a number of different Tegra models and generations, ranging from Tegra K1, to Tegra 210.
Linux
Nvidia distributes proprietary device drivers for Tegra through
OEM
An original equipment manufacturer (OEM) is generally perceived as a company that produces non-aftermarket parts and equipment that may be marketed by another manufacturer. It is a common industry term recognized and used by many professional or ...
s and as part of its "Linux for Tegra" (formerly "L4T") development kit. The newer and more powerful devices of the Tegra family are now supported by Nvidia's own
Vibrante Linux distribution. Vibrante comes with a larger set of Linux tools plus several Nvidia provided libraries for acceleration in the area of data processing and especially image processing for driving safety and automated driving up to the level of deep learning and neuronal networks that make e.g. heavy use of the CUDA capable accelerator blocks, and via
OpenCV
OpenCV (''Open Source Computer Vision Library'') is a library of programming functions mainly aimed at real-time computer vision. Originally developed by Intel, it was later supported by Willow Garage then Itseez (which was later acquired by In ...
can make use of the
NEON vector extensions of the ARM cores.
, due to different "business needs" from that of their
GeForce
GeForce is a brand of graphics processing units (GPUs) designed by Nvidia. As of the GeForce 40 series, there have been eighteen iterations of the design. The first GeForce products were discrete GPUs designed for add-on graphics boards, inte ...
line of graphics cards, Nvidia and one of their Embedded Partners, Avionic Design GmbH from Germany, are also working on submitting
open-source drivers for Tegra upstream to the mainline
Linux kernel.
Nvidia co-founder & CEO laid out the Tegra processor roadmap using Ubuntu Unity in
GPU Technology Conference
Nvidia CorporationOfficially written as NVIDIA and stylized in its logo as VIDIA with the lowercase "n" the same height as the uppercase "VIDIA"; formerly stylized as VIDIA with a large italicized lowercase "n" on products from the mid 1990s to ...
2013.
By end of 2018 it is evident that Nvidia employees have contributed substantial code parts to make the T186 and T194 models run for HDMI display and audio with the upcoming official Linux kernel 4.21 in about Q1 2019. The affected software modules are the open source Nouveau and the closed source Nvidia graphics drivers along with the Nvidia proprietary CUDA interface.
QNX
The Drive PX2 board was announced with
QNX
QNX ( or ) is a commercial Unix-like real-time operating system, aimed primarily at the embedded systems market. QNX was one of the first commercially successful microkernel operating systems.
The product was originally developed in the early ...
RTOS support at the April 2016 GPU Technology Conference.
Similar platforms
SoCs and platforms with comparable specifications (e.g. audio/video input, output and processing capability, connectivity, programmability, entertainment/embedded/automotive capabilities & certifications, power consumption) are:
See also
*
Project Denver
Project Denver is the codename of a central processing unit designed by Nvidia that implements the ARMv8-A 64/ 32-bit instruction sets using a combination of simple hardware decoder and software-based binary translation (dynamic recompilation) ...
*
Nomadik
Nomadik is a family of microprocessors for multimedia applications from STMicroelectronics. It is based on ARM9 ARM architecture and was designed specifically for mobile devices.
On December 12, 2002, STMicroelectronics and Texas Instruments joint ...
*
XScale
XScale is a microarchitecture for central processing units initially designed by Intel implementing the ARM architecture (version 5) instruction set. XScale comprises several distinct families: IXP, IXC, IOP, PXA and CE (see more below), with some ...
*
ZiiLABS
ZiiLABS is a global electronics company, producing a line of media-oriented application processors, reference platforms and enabling software, in a series of platforms named ZMS. Its products are found in low-power consumer electronics and embedded ...
References
External links
Official websiteNvidia's Tegra FAQTegra X1 WhitepaperTegra K1 WhitepaperTegra 4 CPU WhitepaperTegra 4 GPU WhitepaperTegra 3 WhitepaperTegra 2 Whitepaper
{{ARM-based chips
ARM-based systems on chips
Mobile computers
Nvidia hardware
System on a chip