Stub Series Terminated Logic (SSTL) is a group of electrical standards for driving
transmission line
In electrical engineering, a transmission line is a specialized cable or other structure designed to conduct electromagnetic waves in a contained manner. The term applies when the conductors are long enough that the wave nature of the transmi ...
s commonly used with
DRAM based
DDR
DDR or ddr may refer to:
*ddr, ISO 639-3 code for the Dhudhuroa language
*DDr., title for a double doctorate in Germany
*DDR, station code for Dadar railway station, Mumbai, India
*' (German Democratic Republic), official name of the former East ...
memory IC's and memory modules. SSTL is primarily designed for driving the
DDR (double-data-rate) SDRAM modules used in
computer memory
In computing, memory is a device or system that is used to store information for immediate use in a computer or related computer hardware and digital electronic devices. The term ''memory'' is often synonymous with the term '' primary storag ...
; however, it is also used in other applications, notably some
PCI Express PHYs and other high-speed devices.
Four voltage levels for SSTL are defined:
*SSTL_3, 3.3 V, defined in EIA/JESD8-8 1996
*SSTL_2, 2.5 V, defined in EIA/JESD8-9B 2002 used in
DDR
DDR or ddr may refer to:
*ddr, ISO 639-3 code for the Dhudhuroa language
*DDr., title for a double doctorate in Germany
*DDR, station code for Dadar railway station, Mumbai, India
*' (German Democratic Republic), official name of the former East ...
among other things.
*SSTL_18, 1.8 V, defined in EIA/JESD8-15A, used in
DDR2 among other things.
*SSTL_15, 1.5 V, used in
DDR3
Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth (" double data rate") interface, and has been in use since 2007. It is the higher-spee ...
among other things.
SSTL_3 uses a reference of 0.45 * VDDQ (1.5 V). SSTL_2 and SSTL_18 reference a voltage that is exactly VDDQ / 2 (1.25 V and 0.9 V respectively).
[Tom Granberg ''Handbook of Digital Techniques for High-Speed Digital Design''. Pearson Education, 2004, p. 160-161.]
SSTL_3 and SSTL_2 support two termination classes (50 ohm or 25 ohm load). SSTL_18 only supports one (25 ohm load).
See also
*
High-Speed Transceiver Logic - HSTL
References
External links
JEDEC homepage links; require (free) login:
JEDEC SSTL_2 Standard (JESD8-9B)JEDEC SSTL_18 Standard (JESD8-15A)
Computer memory
JEDEC standards
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