Single-event Upsets
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A single-event upset (SEU), also known as a single-event error (SEE), is a change of state caused by one single ionizing particle (ions, electrons, photons...) striking a sensitive node in a live micro-electronic device, such as in a microprocessor,
semiconductor memory Semiconductor memory is a digital electronic semiconductor device used for digital data storage, such as computer memory. It typically refers to devices in which data is stored within metal–oxide–semiconductor (MOS) memory cells on a sili ...
, or power transistors. The state change is a result of the free charge created by ionization in or close to an important node of a logic element (e.g. memory "bit"). The error in device output or operation caused as a result of the strike is called an SEU or a
soft error In electronics and computing, a soft error is a type of error where a signal or datum is wrong. Errors may be caused by a defect, usually understood either to be a mistake in design or construction, or a broken component. A soft error is also a s ...
. The SEU itself is not considered permanently damaging to the transistor's or circuits' functionality unlike the case of single-event
latch-up A latch-up is a type of short circuit which can occur in an integrated circuit (IC). More specifically it is the inadvertent creation of a low- impedance path between the power supply rails of a MOSFET circuit, triggering a parasitic structure whi ...
(SEL), single-event
gate rupture A gate or gateway is a point of entry to or from a space enclosed by walls. The word derived from old Norse "gat" meaning road or path; But other terms include ''yett and port''. The concept originally referred to the gap or hole in the wall ...
(SEGR), or single-event burnout (SEB). These are all examples of a general class of radiation effects in electronic devices called ''single-event effects'' (SEEs).


History

Single-event upsets were first described during above-ground
nuclear testing Nuclear weapons tests are experiments carried out to determine nuclear weapons' effectiveness, yield, and explosive capability. Testing nuclear weapons offers practical information about how the weapons function, how detonations are affected by ...
, from 1954 to 1957, when many anomalies were observed in electronic monitoring equipment. Further problems were observed in space electronics during the 1960s, although it was difficult to separate soft failures from other forms of interference. In 1972, a Hughes satellite experienced an upset where the communication with the satellite was lost for 96 seconds and then recaptured. Scientists Dr. Edward C. Smith, Al Holman, and Dr. Dan Binder explained the anomaly as a single-event upset (SEU) and published the first SEU paper in the IEEE Transactions on Nuclear Science journal in 1975. In 1978, the first evidence of
soft error In electronics and computing, a soft error is a type of error where a signal or datum is wrong. Errors may be caused by a defect, usually understood either to be a mistake in design or construction, or a broken component. A soft error is also a s ...
s from alpha particles in packaging materials was described by
Timothy C. May Timothy C. May, better known as Tim May (December 21, 1951 – December 13, 2018) was an American technical and political writer, and electronic engineer and senior scientist at Intel. May was also the founder of the crypto-anarchist movement. He ...
and M.H. Woods. In 1979, James Ziegler of IBM, along with W. Lanford of Yale, first described the mechanism whereby a sea-level cosmic ray could cause a single-event upset in electronics. 1979 also saw the world’s first heavy ion "single-event effects" test at a particle accelerator facility, conducted at Lawrence Berkeley National Laboratory'
88-Inch Cyclotron
and Bevatron.


Cause

Terrestrial SEU arise due to cosmic particles colliding with atoms in the atmosphere, creating cascades or showers of neutrons and protons, which in turn may interact with electronic circuits. At deep sub-micron geometries, this affects semiconductor devices in the atmosphere. In space, high-energy ionizing particles exist as part of the natural background, referred to as galactic cosmic rays (GCR). Solar particle events and high-energy protons trapped in the Earth's
magnetosphere In astronomy and planetary science, a magnetosphere is a region of space surrounding an astronomical object in which charged particles are affected by that object's magnetic field. It is created by a celestial body with an active interior dynam ...
( Van Allen radiation belts) exacerbate this problem. The high energies associated with the phenomenon in the space particle environment generally render increased spacecraft shielding useless in terms of eliminating SEU and catastrophic single-event phenomena (e.g. destructive
latch-up A latch-up is a type of short circuit which can occur in an integrated circuit (IC). More specifically it is the inadvertent creation of a low- impedance path between the power supply rails of a MOSFET circuit, triggering a parasitic structure whi ...
). Secondary atmospheric neutrons generated by cosmic rays can also have sufficiently high energy for producing SEUs in electronics on aircraft flights over the poles or at high altitude. Trace amounts of radioactive elements in chip packages also lead to SEUs.


Testing for SEU sensitivity

The sensitivity of a device to SEU can be empirically estimated by placing a test device in a particle stream at a cyclotron or other particle accelerator facility. This particular test methodology is especially useful for predicting the SER (soft error rate) in known space environments, but can be problematic for estimating terrestrial SER from neutrons. In this case, a large number of parts must be evaluated, possibly at different altitudes, to find the actual rate of upset. Another way to empirically estimate SEU tolerance is to use a chamber shielded for radiation, with a known radiation source, such as Caesium-137. When testing microprocessors for SEU, the software used to exercise the device must also be evaluated to determine which sections of the device were activated when SEUs occurred.


SEUs and circuit design

By definition, SEUs do not destroy the circuits involved, but they can cause errors. In space-based microprocessors, one of the most vulnerable portions is often the 1st and 2nd-level cache memories, because these must be very small and have very high-speed, which means that they do not hold much charge. Often these caches are disabled if terrestrial designs are being configured to survive SEUs. Another point of vulnerability is the state machine in the microprocessor control, because of the risk of entering "dead" states (with no exits), however, these circuits must drive the entire processor, so they have relatively large transistors to provide relatively large electric currents and are not as vulnerable as one might think. Another vulnerable processor component is the RAM. To ensure resilience to SEUs, often an error correcting memory is used, together with circuitry to periodically read (leading to correction) or
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(if reading does not lead to correction) the memory of errors, before the errors overwhelm the error-correcting circuitry. In digital and analog circuits, a single event may cause one or more voltages pulses (i.e. glitches) to propagate through the circuit, in which case it is referred to as a single-event transient (SET). Since the propagating pulse is not technically a change of "state" as in a memory SEU, one should differentiate between SET and SEU. If a SET propagates through digital circuitry and results in an incorrect value being latched in a sequential logic unit, it is then considered an SEU. Hardware problems can also occur for related reasons. Under certain circumstances (of both circuit design, process design, and particle properties) a " parasitic" thyristor inherent to CMOS designs can be activated, effectively causing an apparent short-circuit from power to ground. This condition is referred to as ''
latch-up A latch-up is a type of short circuit which can occur in an integrated circuit (IC). More specifically it is the inadvertent creation of a low- impedance path between the power supply rails of a MOSFET circuit, triggering a parasitic structure whi ...
'', and in absence of constructional countermeasures, often destroys the device due to thermal runaway. Most manufacturers design to prevent latch-up, and test their products to ensure that latch-up does not occur from atmospheric particle strikes. In order to prevent latch-up in space, epitaxial substrates,
silicon on insulator In semiconductor manufacturing, silicon on insulator (SOI) technology is fabrication of silicon semiconductor devices in a layered silicon–insulator–silicon substrate, to reduce parasitic capacitance within the device, thereby improving perfo ...
(SOI) or silicon on sapphire (SOS) are often used to further reduce or eliminate the susceptibility.


Notable SEU

* In the 2003 elections in Brussels's municipality Schaerbeek ( Belgium), an anomalous recorded number of votes triggered an investigation that concluded an SEU was responsible for giving a candidate named
Maria Vindevoghel Maria Vindevoghel (born 11 October 1957) is a Belgian shop steward in the Confederation of Christian Trade Unions and politician of the Workers' Party of Belgium. Biography Maria Vindevoghel grew up in a farming family in West Flanders. At 20, ...
4,096 extra votes. The possibility of a single-event upset is suggested by the difference in votes being equivalent to a power of two, . * In 2013, a speedrunner of the video game
Super Mario 64 is a platform game developed and published by Nintendo for the Nintendo 64. It was released in Japan and North America in 1996 and PAL regions in 1997. It is the first ''Super Mario'' game to feature 3D gameplay, combining traditional ''Su ...
using the Nintendo 64 console experienced a glitch that teleported Mario higher up in the "Tick Tock Clock" stage. This has been hypothesized to have been caused by an SEU, flipping the least significant bit of Mario’s height value's most significant byte. Other players reproduced the exact controller inputs to recreate the speedrun identically without the same effect, only manually editing the specific memory value in the memory editor of an emulator can replicate the glitch.


See also

* Radiation hardening * Cosmic rays * Hamming distance *
Parity bit A parity bit, or check bit, is a bit added to a string of binary code. Parity bits are a simple form of error detecting code. Parity bits are generally applied to the smallest units of a communication protocol, typically 8-bit octets (bytes) ...
*
Gray code The reflected binary code (RBC), also known as reflected binary (RB) or Gray code after Frank Gray, is an ordering of the binary numeral system such that two successive values differ in only one bit (binary digit). For example, the representati ...
* / * Johnson counter *
Soft error In electronics and computing, a soft error is a type of error where a signal or datum is wrong. Errors may be caused by a defect, usually understood either to be a mistake in design or construction, or a broken component. A soft error is also a s ...


References


Further reading

;General SEU * T.C. May and M.H. Woods, IEEE Trans Electron Devices ED-26, 2 (1979)
www.seutest.com
- Soft-error testing resources to support the JEDEC JESD89A test protocol. * J. F. Ziegler and W. A. Lanford, "Effect of Cosmic Rays on Computer Memories", ''Science'', 206, 776 (1979)

* ttp://radhome.gsfc.nasa.gov/radhome/see.htm NASA Introduction to SEUfrom
Goddard Space Flight Center The Goddard Space Flight Center (GSFC) is a major NASA space research laboratory located approximately northeast of Washington, D.C. in Greenbelt, Maryland, United States. Established on May 1, 1959 as NASA's first space flight center, GSFC empl ...
Radiation Effects Facility
NASA/Smithsonian abstract search
* "Estimating Rates of Single-Event Upsets", J. Zoutendyk, ''NASA Tech Brief'', Vol. 12, No. 10, item #152, Nov. 1988.
Boeing Radiation Effects Laboratory, focussed on Avionics


* [http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=6187516 A Highly Reliable SEU Hardened Latch and High Performance SEU Hardened Flip-Flop, International Symposium on Quality Electronic Design (ISQED), California, USA, March 19--21, 2012] ;SEU in programmable logic devices * "Single-Event Upsets: Should I Worry?" Xilinx Corp. * "Virtex-4: Soft Errors Reduced by Nearly Half!" A. Lesea, Xilinx TecXclusive, 6 May 2005.
Single Event Upsets
Altera Corp.
Evaluation of LSI Soft Errors Induced by Terrestrial Cosmic rays and Alpha Particles
- H. Kobayashi, K. Shiraishi, H. Tsuchiya, H. Usuki (all of Sony), and Y. Nagai, K. Takahisa (Osaka University), 2001.
SEU-Induced Persistent Error Propagation in FPGAs
K. Morgan (Brigham Young University), Aug. 2006.
Microsemi neutron immune FPGA technology.
;SEU in microprocessors * Elder, J.H.; Osborn, J.; Kolasinski, W. A.; "A method for characterizing a microprocessor's vulnerability to SEU", ''IEEE Transactions on Nuclear Science'', Dec 1988 v 35 n 6.
SEU Characterization of Digital Circuits Using Weighted Test Programs

Analysis of Application Behavior During Fault Injection


;SEU related masters theses and doctoral dissertations * * * * * * {{cite book , author=A. G. Costantine, title=An Advanced Single Event Upset Tester, publisher=Rensselaer Polytechnic Institute (Ph. D Thesis) , year=1990 Digital electronics