Hexagon is the brand name for a family of digital signal processor (DSP) products by Qualcomm. Hexagon is also known as QDSP6, standing for “sixth generation digital signal processor.” According to Qualcomm, the Hexagon architecture is designed to deliver performance with low power over a variety of applications. Each version of Hexagon has an instruction set and a micro-architecture. These two features are intimately related. Hexagon is used in Qualcomm Snapdragon chips, for example in smartphones, cars, wearable devices and other mobile devices and is also used in components of cellular phone networks.

Instruction set architecture

Computing devices have instruction sets, which are their lowest, most primitive languages. Common instructions are those which cause two numbers to be added, multiplied or combined in other ways, as well as instructions that direct the processor where to look in memory for its next instruction. There are many other types of instructions. Assemblers and compilers that translate computer programs into streams of instructions – bit streams - that the device can understand and carry out (execute). As an instruction stream executes, the integrity of system function is supported by the use of instruction privilege levels. Privileged instructions have access to more resources in the device, including memory. Hexagon supports privilege levels. Originally, Hexagon instructions operated on integer numbers but not floating point numbers, but in v5 floating point support was added. The processing unit which handles execution of instructions is capable of in-order dispatching up to 4 instructions (the packet) to 4

Execution Units In computer engineering, an execution unit (E-unit or EU) is a part of the central processing unit (CPU) that performs the operations and calculations as instructed by the computer program. It may have its own internal control sequence unit (not ...

every clock.Porting LLVM to a Next Generation DSP
L. Taylor Simpson (Qualcomm) // LLVM Developers’ Meeting: 11/18/2011

Micro-architecture

Micro-architecture is the physical structure of a chip or chip component that makes it possible for a device to carry out the instructions. A given instruction set can be implemented by a variety of micro-architectures. The buses – data transfer channels – for Hexagon devices are 32 bits wide. That is, 32 bits of data can be moved from one part of the chip to another in a single step. The Hexagon micro-architecture is multi-threaded, which means that it can simultaneously process more than one stream of instructions, enhancing data processing speed. Hexagon supports very long instruction words, which are groupings of four instructions that can be executed “in parallel.” Parallel execution means that multiple instructions can run simultaneously without one instruction having to complete before the next one starts. The Hexagon micro-architecture supports single instruction, multiple data operations, which means that a when a Hexagon device receives an instruction it can carry out the operation on more than one piece of data at the same time According to 2012 estimation, Qualcomm shipped 1.2 billion DSP cores inside its system on a chip (SoCs) (average 2.3 DSP core per SoC) in 2011, and 1.5 billion cores were planned for 2012, making the QDSP6 the most shipped architecture of DSP (

CEVA Ceva, the ancient Ceba, is a small Italian town in the province of Cuneo, region of Piedmont, east of Cuneo. It lies on the right bank of the Tanaro on a wedge of land between that river and the Cevetta stream. History In the pre-Roman period t ...

had around 1 billion of DSP cores shipped in 2011 with 90% of IP-licenseable DSP market). The Hexagon architecture is designed to deliver performance with low power over a variety of applications. It has features such as hardware assisted multithreading, privilege levels, Very Long Instruction Word (VLIW), Single Instruction Multiple Data (SIMD), and instructions geared toward efficient signal processing. Hardware multithreading is implemented as barrel

temporal multithreading Temporal multithreading is one of the two main forms of multithreading that can be implemented on computer processor hardware, the other being simultaneous multithreading. The distinguishing difference between the two forms is the maximum number ...

- threads are switched in round-robin fashion each cycle, so the 600 MHz physical core is presented as three logical 200 MHz cores before V5. Hexagon V5 switched to dynamic multithreading (DMT) with thread switch on L2 misses, interrupt waiting or on special instructions.Qualcomm Extends Hexagon DSP: Hexagon v5 Adds Floating-Point Math, Dynamic Multithreading
// Linley Gwennap, Microprocessor Report, August 2013 At Hot Chips 2013 Qualcomm announced details of their Hexagon 680 DSP. Qualcomm announced Hexagon Vector Extensions (HVX). HVX is designed to allow significant compute workloads for advanced imaging and computer vision to be processed on the DSP instead of the CPU. In March 2015 Qualcomm announced their Snapdragon Neural Processing Engine SDK which allow AI acceleration using the CPU, GPU and Hexagon DSP. Qualcomm's Snapdragon 855 contains their 4th generation on-device AI engine, which includes the Hexagon 690 DSP and Hexagon Tensor Accelerator (HTA) for AI acceleration.

Software support

Operating systems

The

port A port is a maritime facility comprising one or more wharves or loading areas, where ships load and discharge cargo and passengers. Although usually situated on a sea coast or estuary, ports can also be found far inland, such as Ham ...

Linux Linux ( or ) is a family of open-source Unix-like operating systems based on the Linux kernel, an operating system kernel first released on September 17, 1991, by Linus Torvalds. Linux is typically packaged as a Linux distribution, which ...

for Hexagon runs under a

hypervisor A hypervisor (also known as a virtual machine monitor, VMM, or virtualizer) is a type of computer software, firmware or hardware that creates and runs virtual machines. A computer on which a hypervisor runs one or more virtual machines is calle ...

layer ("Hexagon Virtual Machine") and was merged with the 3.2 release of the

kernel Kernel may refer to: Computing * Kernel (operating system), the central component of most operating systems * Kernel (image processing), a matrix used for image convolution * Compute kernel, in GPGPU programming * Kernel method, in machine learn ...

. The original hypervisor is closed-source, and in April 2013 a minimal open-source hypervisor implementation for QDSP6 V2 and V3, the "Hexagon MiniVM" was released by Qualcomm under a

BSD-style license BSD licenses are a family of permissive free software licenses, imposing minimal restrictions on the use and distribution of covered software. This is in contrast to copyleft licenses, which have share-alike requirements. The original BSD lice ...

Compilers

Support for Hexagon was added in 3.1 release of

LLVM LLVM is a set of compiler and toolchain technologies that can be used to develop a front end for any programming language and a back end for any instruction set architecture. LLVM is designed around a language-independent intermediate repre ...

by Tony Linthicum. Hexagon/HVX V66 ISA support was added in 8.0.0 release of

. There is also a non- FSF maintained branch of GCC and

binutils The GNU Binary Utilities, or , are a set of programming tools for creating and managing binary programs, object files, libraries, profile data, and assembly source code. Tools They were originally written by programmers at Cygnus Solutions. ...

Adoption of the SIP block

Qualcomm Hexagon DSPs have been available in Qualcomm Snapdragon SoC since 2006.Qualcomm Announces Its 2012 Superchip: 28nm Snapdragon S4
10/12/2011 by John Oram. Quote: "Hexagon DSPs have been in Snapdragon chips since 2006."QDSP6 V4: Qualcomm Gives Customers and Developers Programming Access to its DSP Core
// InsideDSP, June 22, 2012 In Snapdragon S4 (MSM8960 and newer) there are three QDSP cores, two in the Modem subsystem and one Hexagon core in the Multimedia subsystem. Modem cores are programmed by Qualcomm only, and only Multimedia core is allowed to be programmed by user. They are also used in some

femtocell In telecommunications, a femtocell is a small, low-power cellular base station, typically designed for use in a home or small business. A broader term which is more widespread in the industry is '' small cell'', with ''femtocell'' as a subset. It ...

processors of Qualcomm, including FSM98xx, FSM99xx and FSM90xx.

Third-party integration

In March 2016, it was announced that semiconductor company

Conexant Conexant Systems, Inc. was an American-based software developer and fabless semiconductor company that developed technology for voice and audio processing, imaging and modems. The company began as a division of Rockwell International, before ...

's AudioSmart audio processing software was being integrated into Qualcomm's Hexagon. In May 2018

wolfSSL wolfSSL is a small, portable, embedded SSL/TLS library targeted for use by embedded systems developers. It is an open source implementation of TLS (SSL 3.0, TLS 1.0, 1.1, 1.2, 1.3, and DTLS 1.0, 1.2, and 1.3) written in the C programming lan ...

added support for using Qualcomm Hexagon. This is support for running wolfSSL crypto operations on the DSP. In addition to use of crypto operations a specialized operation load management library was later added.

Versions

There are six versions of QDSP6 architecture released: V1 (2006), V2 (2007–2008), V3 (2009), V4 (2010–2011), QDSP6 V5 (2013, in Snapdragon 800Qualcomm Announces Next Generation Snapdragon Premium Mobile Processors
/ Qualcomm, January 07, 2013); and QDSP6 V6 (2016, in Snapdragon 820). V4 has 20 DMIPS per milliwatt, operating at 500 MHz. Clock speed of Hexagon varies in 400–2000 MHz for QDSP6 and in 256–350 MHz for previous generation of the architecture, the QDSP5.

Availability in Snapdragon products

Both Hexagon (QDSP6) and pre-Hexagon (QDSP5) cores are used in modern Qualcomm SoCs, QDSP5 mostly in low-end products. Modem QDSPs (often pre-Hexagon) are not shown in the table. QDSP5 usage: QDSP6 (Hexagon) usage:

Hardware codec supported

The different video codecs supported by the Snapdragon SoCs. D - decode; E - encode FHD = FullHD = 1080p = 1920x1080px HD = 720p which can be 1366x768px or 1280x720px

Snapdragon 200 series

The different video codecs supported by the Snapdragon 200 series.

Snapdragon 400 series

The different video codecs supported by the Snapdragon 400 series.

Snapdragon 600 series

The different video codecs supported by the Snapdragon 600 series.

Snapdragon 700 series

The different video codecs supported by the Snapdragon 700 series.

Snapdragon 800 series

The different video codecs supported by the Snapdragon 800 series.

Code sample

This is a single instruction packet from the inner loop of a

FFT A fast Fourier transform (FFT) is an algorithm that computes the discrete Fourier transform (DFT) of a sequence, or its inverse (IDFT). Fourier analysis converts a signal from its original domain (often time or space) to a representation in the ...

:endloop0

This packet is claimed by Qualcomm to be equal to 29 classic RISC operations; it includes vector add (4x 16-bit), complex multiply operation and hardware loop support. All instructions of the packet are done in the same cycle.

References

{{Reflist, 30em

External links

Qualcomm's Hexagon home page

Upcoming DSP architectures
Arnd Bergmann // LWN
Introduction to Qualcomm’s QDSP Access Program
// Qualcomm, 2011
Qualcomm Hexagon DSP: An architecture optimized for mobile multimedia and communications
// Lucian Codrescu (Qualcomm), Hot Chips 25, Palo Alto, CA, August 2013.
Qualcomm Extends Hexagon DSP: Hexagon v5 Adds Floating-Point Math, Dynamic Multithreading
// Linley Gwennap, Microprocessor Report, August 2013. Digital signal processors Instruction set architectures Qualcomm IP cores Very long instruction word computing