POWER7 is a family of
superscalar multi-core microprocessor
A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit, or a small number of integrated circuits. The microprocessor contains the arithmetic, logic, and control circu ...
s based on the
Power ISA 2.06 instruction set architecture
In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an ' ...
released in 2010 that succeeded the
POWER6
The POWER6 is a microprocessor developed by IBM that implemented the Power ISA v.2.03. When it became available in systems in 2007, it succeeded the POWER5+ as IBM's flagship Power microprocessor. It is claimed to be part of the eCLipz projec ...
and
POWER6+. POWER7 was developed by
IBM at several sites including IBM's
Rochester, MN
Rochester is a city in the U.S. state of Minnesota and the county seat of Olmsted County. Located on rolling bluffs on the Zumbro River's south fork in Southeast Minnesota, the city is the home and birthplace of the renowned Mayo Clinic.
Accor ...
; Austin, TX;
Essex Junction, VT;
T. J. Watson Research Center, NY;
Bromont, QC and IBM Deutschland Research & Development GmbH,
Böblingen
Böblingen (; Swabian German, Swabian: ''Beblenga'') is a town in Baden-Württemberg, Germany, seat of Böblingen (district), Böblingen District. Sindelfingen and Böblingen are Geographic contiguity, contiguous.
History
Böblingen was found ...
, Germany laboratories. IBM announced servers based on POWER7 on 8 February 2010.
History
IBM won a $244 million
DARPA
The Defense Advanced Research Projects Agency (DARPA) is a research and development agency of the United States Department of Defense responsible for the development of emerging technologies for use by the military.
Originally known as the Adv ...
contract in November 2006 to develop a
petascale
Petascale computing refers to computing systems capable of calculating at least 1015 floating point operations per second (1 petaFLOPS). Petascale computing allowed faster processing of traditional supercomputer applications. The first system ...
supercomputer
A supercomputer is a computer with a high level of performance as compared to a general-purpose computer. The performance of a supercomputer is commonly measured in floating-point operations per second ( FLOPS) instead of million instructions ...
architecture before the end of 2010 in the
HPCS project. The contract also states that the architecture shall be available commercially. IBM's proposal,
PERCS
PERCS (Productive, Easy-to-use, Reliable Computing System) is IBM's answer to DARPA's High Productivity Computing Systems (HPCS) initiative. The program resulted in commercial development and deployment of the Power 775, a supercomputer design ...
(Productive, Easy-to-use, Reliable Computer System), which won them the contract, is based on the POWER7 processor,
AIX
Aix or AIX may refer to:
Computing
* AIX, a line of IBM computer operating systems
*An Alternate Index, for a Virtual Storage Access Method Key Sequenced Data Set
* Athens Internet Exchange, a European Internet exchange point
Places Belgi ...
operating system and
General Parallel File System
GPFS (General Parallel File System, brand name IBM Spectrum Scale) is high-performance clustered file system software developed by IBM. It can be deployed in shared-disk or shared-nothing distributed parallel modes, or a combination of these. I ...
.
One feature that IBM and DARPA collaborated on is modifying the addressing and page table hardware to support global shared memory space for POWER7 clusters. This enables research scientists to program a cluster as if it were a single system, without using message passing. From a productivity standpoint, this is essential since some scientists are not conversant with
MPI or other parallel programming techniques used in clusters.
Design
The POWER7
superscalar multi-core architecture was a substantial evolution from the POWER6 design, focusing more on power efficiency through multiple cores and
simultaneous multithreading
Simultaneous multithreading (SMT) is a technique for improving the overall efficiency of superscalar CPUs with hardware multithreading. SMT permits multiple independent threads of execution to better use the resources provided by modern process ...
(SMT). The POWER6 architecture was built from the ground up to maximize processor frequency at the cost of power efficiency. It achieved a remarkable 5 GHz. While the POWER6 features a
dual-core
A multi-core processor is a microprocessor on a single integrated circuit with two or more separate processing units, called cores, each of which reads and executes program instructions. The instructions are ordinary CPU instructions (such ...
processor, each capable of two-way
simultaneous multithreading
Simultaneous multithreading (SMT) is a technique for improving the overall efficiency of superscalar CPUs with hardware multithreading. SMT permits multiple independent threads of execution to better use the resources provided by modern process ...
(SMT), the IBM POWER 7 processor has up to eight cores, and four threads per core, for a total capacity of 32 simultaneous threads.
IBM stated at ISCA 29 that peak performance was achieved by high frequency designs with 10–20
FO4
In digital electronics, Fan-out of 4 is a measure of time used in digital CMOS technologies: the gate delay of a component with a fan-out of 4.
Fan out = Cload / Cin, where
:Cload = total MOS gate capacitance driven by the logic gate under con ...
delays per
pipeline
Pipeline may refer to:
Electronics, computers and computing
* Pipeline (computing), a chain of data-processing stages or a CPU optimization found on
** Instruction pipelining, a technique for implementing instruction-level parallelism within a s ...
stage at the cost of power efficiency. However, the POWER6 binary floating-point unit achieves a "6-cycle, 13-
FO4
In digital electronics, Fan-out of 4 is a measure of time used in digital CMOS technologies: the gate delay of a component with a fan-out of 4.
Fan out = Cload / Cin, where
:Cload = total MOS gate capacitance driven by the logic gate under con ...
pipeline".
Therefore, the pipeline for the POWER7 CPU has been changed again, just as it was for the POWER5 and POWER6 designs. In some respects, this rework is similar to Intel's turn in 2005 that left the P4 7th-generation x86 microarchitecture.
Specifications
The POWER7 is available with 4, 6, or 8 physical cores per microchip, in a 1 to 32-way design, with up to 1024 SMTs and a slightly different
microarchitecture and interfaces for supporting extended/Sub-Specifications in reference to the Power ISA and/or different system architectures. For example, in the Supercomputing (HPC) System Power 775 it is packaged as a 32-way quad-chip-module (QCM) with 256 physical cores and 1024 SMTs. There is also a special
TurboCore mode that can turn off half of the cores from an eight-core processor, but those 4 cores have access to all the memory controllers and L3
cache
Cache, caching, or caché may refer to:
Places United States
* Cache, Idaho, an unincorporated community
* Cache, Illinois, an unincorporated community
* Cache, Oklahoma, a city in Comanche County
* Cache, Utah, Cache County, Utah
* Cache County ...
at increased clock speeds. This makes each core's performance higher which is important for workloads which require the fastest sequential performance at the cost of reduced parallel performance. TurboCore mode can reduce "software costs in half for those applications that are licensed per core, while increasing per core performance from that software."
The new IBM Power 780 scalable, high-end servers featuring the new TurboCore workload optimizing mode and delivering up to double performance per core of POWER6 based systems.
Each core is capable of four-way simultaneous multithreading (SMT). The POWER7 has approximately 1.2 billion transistors and is 567 mm
2 large fabricated on a 45 nm process. A notable difference from POWER6 is that the POWER7 executes instructions out-of-order instead of in-order. Despite the decrease in maximum frequency compared to POWER6 (4.25 GHz vs 5.0 GHz), each core has higher performance than the POWER6, while each processor has up to 4 times the number of cores.
POWER7 has these specifications:
*
45 nm SOI
''Soi'' ( th, ซอย ) is the term used in Thailand for a side-street branching off a major street (''thanon'', th, ถนน). An alley is called a ''trok'' ( th, ตรอก).
Overview
Sois are usually numbered, and are referred to by th ...
process, 567 mm
2
* 1.2 billion
transistor
upright=1.4, gate (G), body (B), source (S) and drain (D) terminals. The gate is separated from the body by an insulating layer (pink).
A transistor is a semiconductor device used to Electronic amplifier, amplify or electronic switch, switch e ...
s
* 3.0–4.25 GHz clock speed
* max 4 chips per
quad-chip module
** 4, 6 or 8 C1 cores per chip
*** 4 SMT
threads per C1 core (available in AIX 6.1 TL05 (releases in April 2010) and above)
*** 12 execution units per C1 core:
**** 2 fixed-point units
**** 2 load/store units
**** 4 double-precision floating-point units
**** 1 vector unit supporting
VSX
**** 1 decimal floating-point unit
**** 1 branch unit
**** 1 condition register unit
** 32+32 KB L1 instruction and data cache (per core)
** 256 KB L2 Cache (per C1 core)
** 4 MB L3 cache per C1 core with maximum up to 32 MB supported. The cache is implemented in
eDRAM, which does not require as many transistors per cell as a standard
SRAM so it allows for a larger cache while using the same area as SRAM.
The technical specification further specifies:
Each POWER7 processor core implements aggressive out-of-order (OoO) instruction execution to drive high efficiency in the use of available execution paths. The POWER7 processor has an Instruction Sequence Unit that is capable of dispatching up to six instructions per cycle to a set of queues. Up to eight instructions per cycle can be issued to the Instruction Execution units.
This gives the following theoretical
single precision
Single-precision floating-point format (sometimes called FP32 or float32) is a computer number format, usually occupying 32 bits in computer memory; it represents a wide dynamic range of numeric values by using a floating radix point.
A floating- ...
(SP) performance figures (based on a 4.14 GHz 8 core implementation):
* max 99.36 GFLOPS per core
* max 794.88 GFLOPS per chip
4 64-bit SIMD units per core, and a 128-bit SIMD VMX unit per core, can do 12 Multiply-Adds per cycle, giving 24 SP FP ops per cycle. At 4.14 GHz, that gives 4.14 billion * 24 = 99.36 SP GFLOPS, and at 8 cores, 794.88 SP GFLOPS.
Peak
double precision
Double-precision floating-point format (sometimes called FP64 or float64) is a floating-point number format, usually occupying 64 bits in computer memory; it represents a wide dynamic range of numeric values by using a floating radix point.
Flo ...
(DP) performance is roughly half of peak SP performance.
For comparison, Intel's 2013
Haswell architecture CPUs can do 16 DP FLOPs or 32 SP FLOPs per cycle (8/16 DP/SP
fused multiply-add
Fuse or FUSE may refer to:
Devices
* Fuse (electrical), a device used in electrical systems to protect against excessive current
** Fuse (automotive), a class of fuses for vehicles
* Fuse (hydraulic), a device used in hydraulic systems to protect ...
spread across 2× 256-bit
AVX2
Advanced Vector Extensions (AVX) are extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They were proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge ...
FP vector units). At 3.4 GHz (i7-4770) this translates into 108.8 SP GFLOPS per core and 435.2 SP GFLOPS peak performance across the 4-core chip, giving roughly similar levels of performance per core, without taking into account the effects or benefits of Intel's
Turbo Boost
Intel Turbo Boost is Intel's trade name for central processing units (CPUs) dynamic frequency scaling feature that automatically raises certain versions of its operating frequency when demanding tasks are running, thus enabling a higher resulting ...
technology.
This theoretical peak performance comparison holds in practice too, with the POWER7 and the i7-4770 obtaining similar scores in the
SPEC Spec may refer to:
*Specification (technical standard), an explicit set of requirements to be satisfied by a material, product, or service
**datasheet, or "spec sheet"
People
* Spec Harkness (1887-1952), American professional baseball pitcher
...
CPU2006
floating point
In computing, floating-point arithmetic (FP) is arithmetic that represents real numbers approximately, using an integer with a fixed precision, called the significand, scaled by an integer exponent of a fixed base. For example, 12.345 can be ...
benchmarks (single-threaded): 71.5 for POWER7 versus 74.0 for i7-4770.
Notice that the POWER7 chip significantly outperformed (2×–5×) the i7 in some benchmarks (bwaves, cactusADM, lbm) while also being significantly slower (2x-3x) in most others. This is indicative of major architectural differences between the two chips / mainboards / memory systems etc.: they were designed with different workloads in mind.
However, overall, in a very broad sense, one can say that the floating-point performance of the POWER7 is similar to that of the Haswell i7.
POWER7+
IBM introduced the POWER7+ processor at the
Hot Chips 24 conference in August 2012. It is an updated version with higher speeds, more cache and integrated accelerators. It is manufactured on a 32 nm fabrication process.
The first boxes to ship with the POWER7+ processors were IBM Power 770 and 780 servers. The chips have up to 80 MB of L3 cache (10 MB/core), improved clock speeds (up to 4.4 GHz) and 20
LPAR
A logical partition (LPAR) is a subset of a computer's hardware resources, virtualized as a separate computer. In effect, a physical machine can be partitioned into multiple logical partitions, each hosting a separate instance of an operating ...
s per core.
Products
, the range of POWER7-based systems including
IBM Power Systems
Power Systems is a family of server computers from IBM that are based on its Power processors. It was created in 2008 as a merger of the System p and System i product lines.
History
IBM had two distinct POWER- and PowerPC-based hardware l ...
"Express" models (710, 720, 730, 740 and 750), Enterprise models (770, 780 and 795) and High Performance computing models (755 and 775). Enterprise models differ in having Capacity on Demand capabilities. Maximum specifications are shown in the table below.
IBM also offers 5 POWER7 based
BladeCenter
The IBM BladeCenter was IBM's blade server architecture, until it was replaced by Flex System in 2012. The x86 division was later sold to Lenovo in 2014.
History
Introduced in 2002, based on engineering work started in 1999, the IBM eSe ...
s.
Specifications are shown in the table below.
The following are supercomputer projects that use the POWER7 processor:
*
PERCS
PERCS (Productive, Easy-to-use, Reliable Computing System) is IBM's answer to DARPA's High Productivity Computing Systems (HPCS) initiative. The program resulted in commercial development and deployment of the Power 775, a supercomputer design ...
*
Watson
See also
*
POWER6
The POWER6 is a microprocessor developed by IBM that implemented the Power ISA v.2.03. When it became available in systems in 2007, it succeeded the POWER5+ as IBM's flagship Power microprocessor. It is claimed to be part of the eCLipz projec ...
*
IBM Power microprocessors
IBM Power microprocessors (originally POWER prior to Power10) are designed and sold by IBM for servers and supercomputers. The name "POWER" was originally presented as an acronym for "Performance Optimization With Enhanced RISC". The Power ...
References
External links
IBM POWER7 Systems- IBM POWER7 product page
IBM POWER7 Technology and Systems- IBM Journal of Research and Development (published by IEEE Xplore)
IBM Won DARPA HPCS Phase-IIIIBM Won DARPA HPCS Phase-IIIBM Has Its PERCS
{{DEFAULTSORT:Power7
IBM microprocessors
Power microprocessors
64-bit microprocessors