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A model-specific register (MSR) is any of various
control register A control register is a processor register that changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, and ...
s in the
x86 x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel, based on the 8086 microprocessor and its 8-bit-external-bus variant, the 8088. Th ...
system architecture A system architecture is the conceptual model that defines the structure, behavior, and views of a system. An architecture description is a formal description and representation of a system, organized in a way that supports reasoning about the s ...
used for
debugging In engineering, debugging is the process of finding the Root cause analysis, root cause, workarounds, and possible fixes for bug (engineering), bugs. For software, debugging tactics can involve interactive debugging, control flow analysis, Logf ...
, program execution tracing,
performance A performance is an act or process of staging or presenting a play, concert, or other form of entertainment. It is also defined as the action or process of carrying out or accomplishing an action, task, or function. Performance has evolved glo ...
monitoring, and toggling certain CPU features.


History

With the introduction of the
80386 The Intel 386, originally released as the 80386 and later renamed i386, is the third-generation x86 architecture microprocessor from Intel. It was the first 32-bit processor in the line, making it a significant evolution in the x86 architect ...
processor,
Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, and Delaware General Corporation Law, incorporated in Delaware. Intel designs, manufactures, and sells computer compo ...
began introducing "experimental" features that would not necessarily be present in future versions of the processor. The first of these were two "test registers" (TR6 and TR7) that enabled testing of the processor's
translation lookaside buffer A translation lookaside buffer (TLB) is a memory CPU cache, cache that stores the recent translations of virtual memory address to a physical memory Memory_address, location. It is used to reduce the time taken to access a user memory location. It ...
(TLB); a special variant of the instruction allowed moving to and from the test registers. Three additional test registers followed in the 80486 (TR3–TR5) that enabled testing of the processor's caches for code and data. None of these five registers were implemented in the subsequent Pentium processor; the special variant of generated an invalid
opcode In computing, an opcode (abbreviated from operation code) is an enumerated value that specifies the operation to be performed. Opcodes are employed in hardware devices such as arithmetic logic units (ALUs), central processing units (CPUs), and ...
exception. With the introduction of the
Pentium Pentium is a series of x86 architecture-compatible microprocessors produced by Intel from 1993 to 2023. The Pentium (original), original Pentium was Intel's fifth generation processor, succeeding the i486; Pentium was Intel's flagship proce ...
processor, Intel provided a pair of instructions ( and ) to access current and future "model-specific registers", as well as the instruction to determine which features are present on a particular model. Many of these registers have proven useful enough to be retained. Intel has classified these as ''architectural'' model-specific registers and has committed to their inclusion in future product lines. On modern x86-based systems, the
BIOS In computing, BIOS (, ; Basic Input/Output System, also known as the System BIOS, ROM BIOS, BIOS ROM or PC BIOS) is a type of firmware used to provide runtime services for operating systems and programs and to perform hardware initialization d ...
or
UEFI Unified Extensible Firmware Interface (UEFI, as an acronym) is a Specification (technical standard), specification for the firmware Software architecture, architecture of a computing platform. When a computer booting, is powered on, the UEFI ...
firmware will initialize
CPUID In the x86 architecture, the CPUID instruction (identified by a CPUID opcode) is a processor supplementary instruction (its name derived from " CPU Identification") allowing software to discover details of the processor. It was introduced by Int ...
registers and model-specific registers on each system startup.


Using MSRs

Reading and writing to these registers is handled by the rdmsr and wrmsr instructions, respectively. As these are privileged instructions, they can be executed only by the operating system. Use of the Linux ''msr'' kernel module creates a pseudo file "/dev/cpu/''x''/msr" (with a unique ''x'' for each processor or processor core). A user with permissions to read and/or write to this file can use the file I/O API to access these registers. The ''msr-tools''msr-tools
at 01.org package provides a reference implementation. Documentation regarding which MSRs a certain processor implementation supports is usually found in the processor documentation of the CPU vendor. Examples for rather well-known MSRs are the
memory type range register Memory type range registers (MTRRs) are a set of processor supplementary capability control registers that provide system software with control of how accesses to memory ranges by the CPU are cached. It uses a set of programmable model-speci ...
s (MTRRs) and the address-range registers (ARRs).


See also

*
LOADALL LOADALL is the common name for two different undocumented machine instructions of Intel 80286 and Intel 80386 processors, which allow access to areas of the internal processor state that are normally outside of the IA-32 API scope, like ''descri ...


References

{{Reflist


External links

*https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/best-practices/reading-writing-msrs-in-linux.html * The Intel Model-Specific Registers (MSRs) are described in-depth in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4; the link to the Intel reference manuals (PDFs) download page (which includes Vol 4): https://cdrdv2.intel.com/v1/dl/getContent/671200 Digital registers Instruction processing X86 architecture X86 instructions