Low-Power Double Data Rate (LPDDR), also known as LPDDR SDRAM, is a type of
synchronous dynamic random-access memory
Synchronous dynamic random-access memory (synchronous dynamic RAM or SDRAM) is any DRAM where the operation of its external pin interface is coordinated by an externally supplied clock signal.
DRAM integrated circuits (ICs) produced from the ...
that consumes less power and is targeted for
mobile computers and devices such as mobile phones. Older variants are also known as Mobile DDR, and abbreviated as mDDR.
Modern LPDDR SDRAM is distinct from
DDR SDRAM
Double Data Rate Synchronous Dynamic Random-Access Memory (DDR SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) class of memory integrated circuits used in computers. DDR SDRAM, also retroactively called D ...
, with various differences that make the technology more appropriate for the mobile application.
LPDDR technology standards are developed independently of DDR standards, with LPDDR4X and even LPDDR5 for example being implemented prior to
DDR5 SDRAM
Double Data Rate 5 Synchronous Dynamic Random-Access Memory (DDR5 SDRAM) is a type of synchronous dynamic random-access memory. Compared to its predecessor DDR4 SDRAM, DDR5 was planned to reduce power consumption, while doubling bandwidth. T ...
and offering far higher data rates than
DDR4 SDRAM
Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) is a type of synchronous dynamic random-access memory with a high bandwidth (" double data rate") interface.
Released to the market in 2014, it is a variant of dynamic ran ...
.
Bus width
In contrast with standard SDRAM, used in stationary devices and laptops and usually connected over a 64-bit wide memory bus, LPDDR also permits 16- or 32-bit wide channels.
The "E" versions mark enhanced versions of the specifications. They formalize overclocking the memory array up to 266 MHz for a 33% performance boost. Memory modules implementing these higher frequencies are used in Apple
MacBooks and gaming laptops.
As with standard SDRAM, most generations double the internal fetch size and external transfer speed. (DDR4 and LPDDR5 being the exceptions.)
Generations
LPDDR(1)
The original low-power DDR (sometimes retroactively called LPDDR1) is a slightly modified form of
DDR SDRAM
Double Data Rate Synchronous Dynamic Random-Access Memory (DDR SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) class of memory integrated circuits used in computers. DDR SDRAM, also retroactively called D ...
, with several changes to reduce overall power consumption.
Most significantly, the supply voltage is reduced from 2.5 to 1.8 V. Additional savings come from temperature-compensated refresh (DRAM requires refresh less often at low temperatures), partial array self refresh, and a "deep power down" mode which sacrifices all memory contents. Additionally, chips are smaller, using less board space than their non-mobile equivalents.
Samsung
The Samsung Group (or simply Samsung) ( ko, 삼성 ) is a South Korean multinational manufacturing conglomerate headquartered in Samsung Town, Seoul, South Korea. It comprises numerous affiliated businesses, most of them united under the ...
and
Micron
The micrometre ( international spelling as used by the International Bureau of Weights and Measures; SI symbol: μm) or micrometer ( American spelling), also commonly known as a micron, is a unit of length in the International System of Un ...
are two of the main providers of this technology, which is used in tablet and phone devices such as the
iPhone 3GS
The iPhone 3GS (originally styled iPhone 3G S) is a smartphone that was designed and marketed by Apple Inc. It is the third generation iPhone and the successor to the iPhone 3G. It was unveiled on June 8, 2009 at the WWDC 2009 which took ...
,
original iPad,
Samsung Galaxy Tab 7.0 and
Motorola Droid X.
LPDDR2
In 2009, the standards group
JEDEC
The JEDEC Solid State Technology Association is an independent semiconductor engineering trade organization and standardization body headquartered in Arlington County, Virginia, United States.
JEDEC has over 300 members, including some of the w ...
published JESD209-2, which defined a more dramatically revised low-power DDR interface.
It is not compatible with either DDR1 or
DDR2 SDRAM
Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It superseded the original DDR SDRAM specification, and was itself superseded by DDR3 ...
, but can accommodate either:
* LPDDR2-S2: 2''n'' prefetch memory (like DDR1),
* LPDDR2-S4: 4''n'' prefetch memory (like DDR2), or
* LPDDR2-N: Non-volatile (
NAND flash
Flash memory is an electronic non-volatile computer memory storage medium that can be electrically erased and reprogrammed. The two main types of flash memory, NOR flash and NAND flash, are named for the NOR and NAND logic gates. Both us ...
) memory.
Low-power states are similar to basic LPDDR, with some additional partial array refresh options.
Timing parameters are specified for LPDDR-200 to LPDDR-1066 (clock frequencies of 100 to 533 MHz).
Working at 1.2 V, LPDDR2 multiplexes the control and address lines onto a 10-bit
double data rate
In computing, a computer bus operating with double data rate (DDR) transfers data on both the rising and falling edges of the clock signal. This is also known as double pumped, dual-pumped, and double transition. The term toggle mode is used in ...
CA bus. The commands are similar to
those of normal SDRAM, except for the reassignment of the precharge and burst terminate opcodes:
Column address bit C0 is never transferred, and is assumed to be zero. Burst transfers thus always begin at even addresses.
LPDDR2 also has an active-low chip select (when high, everything is a NOP) and clock enable CKE signal, which operate like SDRAM. Also like SDRAM, the command sent on the cycle that CKE is first dropped selects the power-down state:
* If the chip is active, it freezes in place.
* If the command is a NOP ( low or CA0–2 = HHH), the chip idles.
* If the command is a refresh command (CA0–2 = LLH), the chip enters the self-refresh state.
* If the command is a burst terminate (CA0–2 = HHL), the chip enters the deep power-down state. (A full reset sequence is required when leaving.)
The mode registers have been greatly expanded compared to conventional SDRAM, with an 8-bit address space, and the ability to read them back. Although smaller than a
serial presence detect EEPROM, enough information is included to eliminate the need for one.
S2 devices smaller than 4
Gbit, and S4 devices smaller than 1 Gbit have only four banks. They ignore the BA2 signal, and do not support per-bank refresh.
Non-volatile memory devices do not use the refresh commands, and reassign the precharge command to transfer address bits A20 and up. The low-order bits (A19 and down) are transferred by a following Activate command. This transfers the selected row from the memory array to one of 4 or 8 (selected by the BA bits) row data buffers, where they can be read by a Read command. Unlike DRAM, the bank address bits are not part of the memory address; any address can be transferred to any row data buffer. A row data buffer may be from 32 to 4096 bytes long, depending on the type of memory. Rows larger than 32 bytes ignore some of the low-order address bits in the Activate command. Rows smaller than 4096 bytes ignore some of the high-order address bits in the Read command.
Non-volatile memory does not support the Write command to row data buffers. Rather, a series of control registers in a special address region support Read and Write commands, which can be used to erase and program the memory array.
LPDDR3
In May 2012,
JEDEC
The JEDEC Solid State Technology Association is an independent semiconductor engineering trade organization and standardization body headquartered in Arlington County, Virginia, United States.
JEDEC has over 300 members, including some of the w ...
published the JESD209-3 Low Power Memory Device Standard.
[JESD209-3 LPDDR3 Low Power Memory Device Standard](_blank)
JEDEC Solid State Technology Association In comparison to LPDDR2, LPDDR3 offers a higher data rate, greater bandwidth and power efficiency, and higher memory density. LPDDR3 achieves a data rate of 1600 MT/s and utilizes key new technologies: write-leveling and command/address training, optional on-die termination (ODT), and low-I/O capacitance. LPDDR3 supports both package-on-package (PoP) and discrete packaging types.
The command encoding is identical to LPDDR2, using a 10-bit double data rate CA bus.
However, the standard only specifies 8''n''-prefetch DRAM, and does not include the flash memory commands.
Products using LPDDR3 include the 2013 MacBook Air,
iPhone 5S
The iPhone 5S (stylized and marketed as iPhone 5s) is a smartphone that was designed and marketed by Apple Inc. It is the seventh generation of the iPhone, succeeding the iPhone 5, and unveiled in September 2013, alongside the iPhone 5C.
...
,
iPhone 6,
Nexus 10,
Samsung Galaxy S4
The Samsung Galaxy S4 is an Android smartphone produced by Samsung Electronics as the fourth smartphone of the Samsung Galaxy S series and was first shown publicly on March 14, 2013, at Samsung Mobile Unpacked in New York City. It is the succes ...
(GT-I9500) and Microsoft
Surface Pro 3. LPDDR3 went mainstream in 2013, running at 800 MHz DDR (1600 MT/s), offering bandwidth comparable to PC3-12800
notebook memory in 2011 (12.8 GB/s of bandwidth). To achieve this bandwidth, the controller must implement dual-channel memory. For example, this is the case for the Exynos 5 Dual and the 5 Octa.
An "enhanced" version of the specification called LPDDR3e increases the data rate to 2133 MT/s.
Samsung Electronics
Samsung Electronics Co., Ltd. (, sometimes shortened to SEC and stylized as SΛMSUNG) is a South Korean multinational electronics corporation headquartered in Yeongtong-gu, Suwon, South Korea. It is the pinnacle of the Samsung chaebol, a ...
introduced the first 4
gigabit
The bit is the most basic unit of information in computing and digital communications. The name is a portmanteau of binary digit. The bit represents a logical state with one of two possible values. These values are most commonly represent ...
20 nm-class LPDDR3 modules capable of transmitting data at up to 2,133 MT/s, more than double the performance of the older LPDDR2 which is only capable of 800 MT/s. Various
SoCs from various manufacturers also natively support 800 MHz LPDDR3 RAM. Such include the
Snapdragon 600 and 800 from
Qualcomm as well as some SoCs from the
Exynos
Exynos, formerly Hummingbird (), is a series of ARM-based system-on-chips developed by Samsung Electronics' System LSI division and manufactured by Samsung Foundry. It is a continuation of Samsung's earlier S3C, S5L and S5P line of SoCs.
...
and
Allwinner
Allwinner Technology Co., Ltd is a fabless semiconductor company that designs mixed-signal systems on a chip (SoC). The company is headquartered in Zhuhai, Guangdong, China. It has a sales and technical support office in Shenzhen, Guangdong ...
series.
LPDDR4
On 14 March 2012, JEDEC hosted a conference to explore how future mobile device requirements will drive upcoming standards like LPDDR4. On 30 December 2013, Samsung announced that it had developed the first 20 nm-class 8 gigabit (1 GB) LPDDR4 capable of transmitting data at 3,200 MT/s, thus providing 50 percent higher performance than the fastest LPDDR3 and consuming around 40 percent less energy at 1.1 volts.
On 25 August 2014,
JEDEC
The JEDEC Solid State Technology Association is an independent semiconductor engineering trade organization and standardization body headquartered in Arlington County, Virginia, United States.
JEDEC has over 300 members, including some of the w ...
published the JESD209-4 LPDDR4 Low Power Memory Device Standard.
Significant changes include:
* Doubling of the interface speed, and numerous consequent electrical changes, including changing the I/O standard to low-voltage swing-terminated logic (LVSTL)
* Doubling of the internal prefetch size, and minimum transfer size
* Change from a 10-bit DDR command/address bus to a 6-bit SDR bus
* Change from one 32-bit wide bus to two independent 16-bit wide buses
* Self-refresh is enabled by dedicated commands, rather than being controlled by the CKE line
The standard defines SDRAM packages containing two independent 16-bit access channels, each connected to up to two
dies Dies may refer to:
* Dies (deity), the Roman counterpart of the Greek goddess Hemera, the personification of day, daughter of Nox (Night) and Erebus (Darkness).
* Albert Christoph Dies (1755–1822), German painter, composer, and biographer
* Jos ...
per package. Each channel is 16 data bits wide, has its own control/address pins, and allows access to 8 banks of DRAM. Thus, the package may be connected in three ways:
* Data lines and control connected in parallel to a 16-bit data bus, and only chip selects connected independently per channel.
* To two halves of a 32-bit wide data bus, and the control lines in parallel, including chip select.
* To two independent 16-bit wide data buses
Each die provides 4, 6, 8, 12 or 16
gigabit
The bit is the most basic unit of information in computing and digital communications. The name is a portmanteau of binary digit. The bit represents a logical state with one of two possible values. These values are most commonly represent ...
of memory, half to each channel. Thus, each bank is one sixteenth the device size. This is organized into the appropriate number (16
K to 64 K) of 16384-bit (2048-byte) rows. Extension to 24 and 32 gigabit is planned, but it is not yet decided if this will be done by increasing the number of rows, their width, or the number of banks.
Larger packages providing double width (four channels) and up to four dies per pair of channels (8 dies total per package) are also defined.
Data is accessed in bursts of either 16 or 32 transfers (256 or 512 bits, 32 or 64 bytes, 8 or 16 cycles DDR). Bursts must begin on 64-bit boundaries.
Since the clock frequency is higher and the minimum burst length longer than earlier standards, control signals can be more highly multiplexed without the command/address bus becoming a bottleneck. LPDDR4 multiplexes the control and address lines onto a 6-bit single data rate CA bus. Commands require 2 clock cycles, and operations encoding an address (e.g. activate row, read or write column) require two commands. For example, to request a read from an idle chip requires four commands taking 8 clock cycles: Activate-1, Activate-2, Read, CAS-2.
The chip select line (CS) is active-''high''. The first cycle of a command is identified by chip select being high; it is low during the second cycle.
The CAS-2 command is used as the second half of all commands that perform a transfer across the data bus, and provides low-order column address bits:
* Read commands must begin on a column address which is a multiple of 4; there is no provision for communicating a non-zero C0 or C1 address bit to the memory.
* Write commands must begin on a column address which is a multiple of 16; C2 and C3 must be zero for a write command.
* Mode register read and some multi-purpose commands must also be followed by a CAS-2 command, however all the column bits must be zero (low).
The burst length can be configured to be 16, 32, or dynamically selectable by the BL bit of read and write operations.
One DMI (data mask/invert) signal is associated with each 8 data lines, and can be used to minimize the number of bits driven high during data transfers. When high, the other 8 bits are complemented by both transmitter and receiver. If a byte contains five or more 1 bits, the DMI signal can be driven high, along with three or fewer data lines. As signal lines are terminated low, this reduces power consumption.
(An alternative usage, where DMI is used to limit the number of data lines which ''toggle'' on each transfer to at most 4, minimises crosstalk. This may be used by the memory controller during writes, but is not supported by the memory devices.)
Data bus inversion can be separately enabled for reads and writes. For masked writes (which have a separate command code), the operation of the DMI signal depends on whether write inversion is enabled.
* If DBI on writes is disabled, a high level on DMI indicates that the corresponding data byte is to be ignored and not written
* If DBI on writes is enabled, a ''low'' level on DMI, combined with a data byte with 5 or more bits set, indicates a data byte to be ignored and not written.
LPDDR4 also includes a mechanism for "targeted row refresh" to avoid corruption due to "
row hammer" on adjacent rows. A special sequence of three activate/precharge sequences specifies the row which was activated more often than a device-specified threshold (200,000 to 700,000 per refresh cycle). Internally, the device refreshes
physically adjacent rows rather than the one specified in the activate command.
LPDDR4X
Samsung Semiconductor
Samsung Electronics Co., Ltd. (, sometimes shortened to SEC and stylized as SΛMSUNG) is a South Korean multinational electronics corporation headquartered in Yeongtong-gu, Suwon, South Korea. It is the pinnacle of the Samsung chaebol, acco ...
proposed an LPDDR4 variant that it called LPDDR4X. LPDDR4X is identical to LPDDR4 except additional power is saved by reducing the I/O voltage (Vddq) to 0.6 V from 1.1 V. On 9 January 2017, SK Hynix announced 8 and 16 GB LPDDR4X packages. JEDEC published the LPDDR4X standard on 8 March 2017. Aside from the lower voltage, additional improvements include a single-channel die option for smaller applications, new MCP, PoP and IoT packages, and additional definition and timing improvements for the highest 4266 MT/s speed grade.
LPDDR5
On 19 February 2019,
JEDEC
The JEDEC Solid State Technology Association is an independent semiconductor engineering trade organization and standardization body headquartered in Arlington County, Virginia, United States.
JEDEC has over 300 members, including some of the w ...
published the JESD209-5, Standard for Low Power Double Data Rate 5 (LPDDR5).
Samsung
The Samsung Group (or simply Samsung) ( ko, 삼성 ) is a South Korean multinational manufacturing conglomerate headquartered in Samsung Town, Seoul, South Korea. It comprises numerous affiliated businesses, most of them united under the ...
announced it had working prototype LPDDR5 chips in July 2018. LPDDR5 introduces the following changes:
* Data transfer rate is increased to 6400 Mbit/s.
*
Differential clocks are used
* Prefetch is ''not'' doubled again, but remains 16''n''
* The number of banks is increased to 16, divided into four
DDR4-like bank groups
* Power-saving improvements:
[
** Data-Copy and Write-X (all one or all zero) commands to decrease data transfer
** Dynamic frequency and voltage scaling
* A new clocking architecture called WCK & Read Strobe (RDQS)][
AMD Van Gogh, Intel Tiger Lake, ]Apple silicon
Apple silicon is a series of system on a chip (SoC) and system in a package (SiP) processors designed by Apple Inc., mainly using the ARM architecture. It is the basis of most new Mac computers as well as iPhone, iPad, iPod Touch, Apple ...
(M1 Pro, M1 Max, M1 Ultra, M2 and A16 Bionic), Huawei Kirin 9000 and Snapdragon 888
This is a list of Qualcomm Snapdragon systems on chips (SoC) made by Qualcomm for use in smartphones, tablets, laptops, 2-in-1 PCs, smartwatches, and smartbooks devices.
Before Snapdragon
SoC made by Qualcomm before it was renamed to Snapdr ...
memory controller supports LPDDR5.
LPDDR5X
On 28 July 2021, JEDEC published the JESD209-5B, Standard for Low Power Double Data Rate 5X (LPDDR5X) with the following changes:
* Speed extension up to 8533 Mbit/s
* Signal Integrity improvements with TX/RX equalization
* Reliability improvements via the new Adaptive Refresh Management feature
* Prefetch is still same as LPDDR5 at 16n
On 9 November 2021, Samsung announced that the company has developed the industry's first LPDDR5x DRAM. Samsung's implementation involves 16-gigabit (2GB) dies, on a 14 nm process
The 14 nm process refers to the MOSFET technology node that is the successor to the 22nm (or 20nm) node. The 14nm was so named by the International Technology Roadmap for Semiconductors (ITRS). Until about 2011, the node following 22nm was expe ...
node, with modules with up to 32 dies (64GB) in a single package. According to the company, the new modules would use 20% less power than LPDDR5. According to Andrei Frumusanu of ''AnandTech
''AnandTech'' is an online computer hardware magazine owned by Future plc. It was founded in 1997 by then-14-year-old Anand Lal Shimpi, who served as CEO and editor-in-chief until August 30, 2014, with Ryan Smith replacing him as editor-in-chie ...
'', LPDDR5X in SoCs and other products was expected for the 2023 generation of devices.
On 19 November 2021, Micron announced that Mediatek has validated its LPDDR5X DRAM for Mediatek's Dimensity 9000 5G SoC.
Notes
References
External links
Micron
Nanya
Samsung
* JEDEC pages
LOW POWER DOUBLE DATA RATE 3 SDRAM (LPDDR3)
{{Use dmy dates, date=February 2020
SDRAM