Overview
Memory Dividers allow system memory to run slower than or faster than the actual FSB (Front Side Bus) speed. Ideally, Front Side Bus and system memory should run at the same clock speed because FSB connects system memory to the CPU, but it is sometimes desired to run the FSB and system memory at different clock speeds. It is possible to run FSB and memory clock at different clock speeds, within certain limits of theDescription and application
Usually (Memory Divider) × (Example
Suppose a computer system has DDR memory, a Memory Divider of 1:1, an FSB operating at 200 MHz and a CPU multiplier of 10x. Then, the base memory clock will operate at (Memory Divider) × (FSB) = 1 × 200 = 200 MHz and the effective memory clock would be 400 MHz since it is a DDR system ("DDR" stands for Double Data Rate; the effective memory clock speed is double the actual clock speed). The CPU will operate at 10 × 200 MHz = 2.0 GHz. Using I/O bus frequency of 200 MHz various types ofSee also
*References
1