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{{Short description, Ratio used in computer memory A memory divider is a ratio which is used to determine the operating clock
frequency Frequency is the number of occurrences of a repeating event per unit of time. It is also occasionally referred to as ''temporal frequency'' for clarity, and is distinct from ''angular frequency''. Frequency is measured in hertz (Hz) which is eq ...
of
computer memory In computing, memory is a device or system that is used to store information for immediate use in a computer or related computer hardware and digital electronic devices. The term ''memory'' is often synonymous with the term ''primary storage ...
in accordance with
front side bus A front-side bus (FSB) is a computer communication interface (bus) that was often used in Intel-chip-based computers during the 1990s and 2000s. The EV6 bus served the same function for competing AMD CPUs. Both typically carry data between the ...
(FSB) frequency, if the memory system is dependent on FSB clock speed. Along with
memory latency ''Memory latency'' is the time (the latency) between initiating a request for a byte or word in memory until it is retrieved by a processor. If the data are not in the processor's cache, it takes longer to obtain them, as the processor will hav ...
timings, memory dividers are extensively used in
overclocking In computing, overclocking is the practice of increasing the clock rate of a computer to exceed that certified by the manufacturer. Commonly, operating voltage is also increased to maintain a component's operational stability at accelerated spe ...
memory subsystems to find stable, working memory states at higher FSB frequencies. The ratio between DRAM and FSB is commonly referred to as "DRAM:FSB ratio". Memory dividers are only applicable to those chipsets in which memory speed is dependent on FSB speeds. Certain chipsets like
nVidia Nvidia CorporationOfficially written as NVIDIA and stylized in its logo as VIDIA with the lowercase "n" the same height as the uppercase "VIDIA"; formerly stylized as VIDIA with a large italicized lowercase "n" on products from the mid 1990s to ...
680i have separate memory and FSB lanes due to which memory clock and FSB clock are asynchronous and memory dividers are not used there. Setting memory speeds and overclocking memory systems in such chipsets are different issues which do not use memory dividers. This article is only applicable to those chipsets in which the memory clock is dependent on FSB clock.


Overview

Memory Dividers allow system memory to run slower than or faster than the actual FSB (Front Side Bus) speed. Ideally, Front Side Bus and system memory should run at the same clock speed because FSB connects system memory to the CPU, but it is sometimes desired to run the FSB and system memory at different clock speeds. It is possible to run FSB and memory clock at different clock speeds, within certain limits of the
motherboard A motherboard (also called mainboard, main circuit board, mb, mboard, backplane board, base board, system board, logic board (only in Apple computers) or mobo) is the main printed circuit board (PCB) in general-purpose computers and other expand ...
and corresponding
chipset In a computer system, a chipset is a set of electronic components An electronic component is any basic discrete device or physical entity in an electronic system used to affect electrons or their associated fields. Electronic components are ...
. So, settings termed as Memory Divider or FSB/DRAM settings are available and are expressed in a "ratio" which control the difference in memory clock rate and FSB speed. Entry Level motherboards usually do not provide memory dividers to be changed and the memory dividers are managed by
Memory Controller The memory controller is a digital circuit that manages the flow of data going to and from the computer's main memory. A memory controller can be a separate chip or integrated into another chip, such as being placed on the same die or as an int ...
(if chipset supports memory dividers). High end motherboards meant for
overclocking In computing, overclocking is the practice of increasing the clock rate of a computer to exceed that certified by the manufacturer. Commonly, operating voltage is also increased to maintain a component's operational stability at accelerated spe ...
provide facilities to change memory dividers (if chipset supports memory dividers). However, in certain chipsets memory dividers are not used, because in those systems memory speed is independent of FSB speed.


Description and application

Usually (Memory Divider) × (
Front Side Bus A front-side bus (FSB) is a computer communication interface (bus) that was often used in Intel-chip-based computers during the 1990s and 2000s. The EV6 bus served the same function for competing AMD CPUs. Both typically carry data between the ...
Frequency) gives I/O Bus clock of the memory. Memory clock then determines the final operating frequency or effective clock speed of memory system depending upon DRAM types (DDR, DDR2 and DDR3 SDRAM). By default, FSB speed and memory are usually set to a 1:1 ratio, meaning that increasing FSB speed (by
overclocking In computing, overclocking is the practice of increasing the clock rate of a computer to exceed that certified by the manufacturer. Commonly, operating voltage is also increased to maintain a component's operational stability at accelerated spe ...
) increases memory speed by the same amount. Normally system memory is not built for overclocking and thus may not be able to take the level of overclocking that the processor or motherboard can achieve. The memory divider allows users to mitigate this problem by reducing the speed increase of the memory relative to that of the FSB and the processor.


Example

Suppose a computer system has DDR memory, a Memory Divider of 1:1, an FSB operating at 200 MHz and a CPU multiplier of 10x. Then, the base memory clock will operate at (Memory Divider) × (FSB) = 1 × 200 = 200 MHz and the effective memory clock would be 400 MHz since it is a DDR system ("DDR" stands for Double Data Rate; the effective memory clock speed is double the actual clock speed). The CPU will operate at 10 × 200 MHz = 2.0 GHz. Using I/O bus frequency of 200 MHz various types of
DRAM Dynamic random-access memory (dynamic RAM or DRAM) is a type of random-access semiconductor memory that stores each bit of data in a memory cell, usually consisting of a tiny capacitor and a transistor, both typically based on metal-oxid ...
will operate as:
DDR SDRAM Double Data Rate Synchronous Dynamic Random-Access Memory (DDR SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) class of memory integrated circuits used in computers. DDR SDRAM, also retroactively called DDR1 ...
at 400 MHz (DDR-400 or PC-3200)
DDR2 SDRAM Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It superseded the original DDR SDRAM specification, and was itself superseded by DDR3 ...
at 800 MHz (DDR2-800 or PC2-6400)
DDR3 SDRAM Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth (" double data rate") interface, and has been in use since 2007. It is the higher-speed ...
at 1600 MHz (DDR3-1600 or PC3-12800) Now suppose that we overclock FSB to 250 MHz so that CPU operates at 10 × 250 MHz = 2.5 GHz and memory clock operates at 250 MHz (Memory Divider × FSB). Since DDR-400 RAM is used then effective memory clock (Actual Memory Frequency) will be 500 MHz. A normal DDR-400 SDRAM will fail to work at 500 MHz since it is designed to work at 400 MHz and system will become unstable. But a modern CPU (having overclocking potential) can work at 2.5 GHz (even if it is designed to work at 2 GHz) flawlessly without giving any problem of stability. To keep running overclocked CPU at 2.5 GHz or even at higher speeds (by increasing FSB) we need to slow down memory clock so as to achieve a stable system. For this if we decrease DRAM:FSB ratio to say 4:5 then resulting memory clock speed is (4/5) × 250 MHz = 200 MHz resulting effective clock speed of 400 MHz on DDR-400. So, we are able to operate upon a stable overclocked CPU at 2.5 GHz from 2 GHz without increasing effective memory clock.


See also

*
CPU multiplier In computing, the clock multiplier (or CPU multiplier or bus/core ratio) sets the ratio of an internal CPU clock rate to the externally supplied clock. A CPU with a 10x multiplier will thus see 10 internal cycles (produced by PLL-based frequency ...


References

1
What is Memory Divider
br /> 2
Important Overclocking Concepts
Computer hardware tuning Clock signal