Standard MII
The standard MII features a small set of registers: * Basic Mode Configuration (#0) * Status Word (#1) * PHY Identifier (#2, #3) * Auto-Negotiation Advertisement (#4) * Auto-Negotiation Link Partner Base Page Ability (#5) * Auto-Negotiation Expansion (#6) * Auto-Negotiation Next Page Transmit (#7) * Auto-Negotiation Link Partner Received Next Page (#8) * MASTER-SLAVE Control Register (#9) * MASTER-SLAVE Status Register (#10) * PSE Control register (#11) * PSE Status register (#12) * MMD Access Control Register (#13) * MMD Access Address Data Register (#14) Register #15 is reserved; registers #16 through #31 are vendor-specific. The registers are used to configure the device and to query the current operating mode. The MII Status Word is the most useful datum, since it may be used to detect whether an Ethernet NIC is connected to a network. It contains a bit field with the following information:Transmitter signals
The transmit clock is a free-running clock generated by the PHY based on the link speed (25 MHz for 100 Mbit/s, 2.5 MHz for 10 Mbit/s). The remaining transmit signals are driven by the MAC synchronously on the rising edge of TX_CLK. This arrangement allows the MAC to operate without having to be aware of the link speed. The transmit enable signal is held high during frame transmission and low when the transmitter is idle. Transmit error may be raised for one or more clock periods during frame transmission to request the PHY to deliberately corrupt the frame in some visible way that precludes it from being received as valid. This may be used to abort a frame when some problem is detected after transmission has already started. The MAC may omit the signal if it has no use for this functionality, in which case the signal should be tied low for the PHY. More recently, raising transmit error ''outside'' frame transmission is used to indicate the transmit data lines are being used for special-purpose signalling. Specifically, the data value 0b0001 (held continuously with TX_EN low and TX_ER high) is used to request an EEE-capable PHY to enter low power mode.Receiver signals
The first seven receiver signals are entirely analogous to the transmitter signals, except RX_ER is not optional and used to indicate the received signal could not be decoded to valid data. The receive clock is recovered from the incoming signal during frame reception. When no clock can be recovered (i.e. when the medium is silent), the PHY must present a free-running clock as a substitute. The receive data valid signal (RX_DV) is not required to go high immediately when the frame starts, but must do so in time to ensure the "start of frame delimiter" byte is included in the received data. Some of the preamble nibbles may be lost. Similar to transmit, raising RX_ER outside a frame is used for special signalling. For receive, two data values are defined: 0b0001 to indicate the link partner is in EEE low power mode, and 0b1110 for a ''false carrier'' indication. The CRS and COL signals are asynchronous to the receive clock, and are only meaningful in half-duplex mode. Carrier sense is high when transmitting, receiving, or the medium is otherwise sensed as being in use. If a collision is detected, COL also goes high while the collision persists. In addition, the MAC may weakly pull-up the COL signal, allowing the combination of COL high with CRS low (which a PHY will never produce) to serve as indication of an absent/disconnected PHY.Management signals
MDC and MDIO constitute a synchronous serial data interface similar to I²C. As with I²C, the interface is a multidrop bus so MDC and MDIO can be shared among multiple PHYs.Limitations
The interface requires 18 signals, out of which only two (MDIO and MDC) can be shared among multiple PHYs. This presents a problem, especially for multiport devices; for example, an eight-port switch using MII would need 8 × 16 + 2 = 130 signals.Reduced media-independent interface
Reduced media-independent interface (RMII) is a standard which was developed to reduce the number of signals required to connect a PHY to a MAC. Reducing pin count reduces cost and complexity for network hardware especially in the context ofLimitations
There is no signal which defines whether the interface is in full or half duplex mode, but both the MAC and the PHY need to agree. This must instead be communicated over the serial MDIO/MDC interface. There is also no signal which defines whether the interface is in 10 or 100 Mbit/s mode, so this must also be handled using the MDIO/MDC interface. Version 1.2 of the RMII Consortium specification states that its MDIO/MDC interface is identical to that specified for MII in IEEE 802.3u. Current revisions of IEEE 802.3 specify a standard MDIO/MDC mechanism for negotiating and configuring the link's speed and duplex mode, but it is possible that older PHY devices might have been designed against obsolete versions of the standard, and may therefore use proprietary methods to set speed and duplex. The lack of the RX_ER signal which is not connected on some MACs (such as multiport switches) is dealt with by data replacement on some PHYs to invalidate the CRC. The missing COL signal is derived from AND-ing together the TX_EN and the decoded CRS signal from the CRS_DV line in half duplex mode. This means a slight modification of the definition of CRS: On MII, CRS is asserted for both Rx and Tx frames; on RMII only for Rx frames. This has the consequence that on RMII the two error conditions ''no carrier'' and ''lost carrier'' cannot be detected, and it is difficult or impossible to support shared media such asSignal levels
TTL logic levels are used for or logic. Input high threshold is and low is . The specification states that inputs should be tolerant, however, some popular chips with RMII interfaces are not tolerant. Newer devices may support and logic. The RMII signals are treated as lumped signals rather than transmission lines. However, the IEEE version of the related MII standard specifies trace impedance.AN-1469 datasheetGigabit media-independent interface
The gigabit media-independent interface (GMII) is an interface between the medium access control (MAC) device and the physical layer ( PHY). The interface operates at speeds up to 1000 Mbit/s, implemented using a data interface clocked at 125 MHz with separate eight-bit data paths for receive and transmit, and is backwards compatible with the MII specification and can operate on fall-back speeds of 10 or 100 Mbit/s. The GMII interface was first defined for 1000BASE-X in IEEE 802.3z-1998 as clause 35, and subsequently incorporated into IEEE 802.3-2000 onwards.Transmitter signals
There are two transmitter clocks. The clock used depends on whether the PHY is operating at gigabit or 10/100 Mbit/s speeds. For gigabit operation, the GTXCLK is supplied to the PHY and the TXD, TXEN, TXER signals are synchronized to this. For 10 or 100 Mbit/s operation, the TXCLK is supplied by the PHY and is used for synchronizing those signals. This operates at either 25 MHz for 100 Mbit/s or 2.5 MHz for 10 Mbit/s connections. In contrast, the receiver uses a single clock signal recovered from the incoming data.Receiver signals
Management signals
The management interface controls the behavior of the PHY. It has the same set of registers as the MII, except that register #15 is the Extended Status register.Reduced gigabit media-independent interface
The reduced gigabit media-independent interface (RGMII) uses half the number of data pins as are used in the GMII interface. This reduction is achieved by running half as many data lines at double speed, time multiplexing signals and by eliminating non-essential carrier-sense and collision-indication signals. Thus RGMII consists only of 14 pins, as opposed to GMII's 24 to 27. Data is clocked on rising and falling edges for 1000 Mbit/s, and on rising edges only for 10/100 Mbit/s. The RX_CTL signal carries RXDV (data valid) on the rising edge, and (RXDV xor RXER) on the falling edge. The TX_CTL signal likewise carries TXEN on rising edge and (TXEN xor TXER) on the falling edge. This is the case for both 1000 Mbit/s and 10/100 Mbit/s. The transmit clock signal is always provided by the MAC on the TXC line. The receive clock signal is always provided by the PHY on the RXC line.Serial gigabit media-independent interface
The serial gigabit media-independent interface (SGMII) is a variant of MII used for Gigabit Ethernet but can also carry 10/100 Mbit/s Ethernet. It uses differential pairs at 625 MHz clock frequency DDR for TX and RX data and TX and RX clocks. It differs from GMII by its low-power and low pin-count 8b/10b-coded SerDes. Transmit and receive path each use one differential pair for data and another differential pair for clock. The TX/RX clocks must be generated on device output but are optional on device input ( clock recovery may be used alternatively). 10/100 Mbit/s Ethernet is carried by duplicating data words 100/10 times each, so the clock is always at 625 MHz.High serial gigabit media independent interface
The high serial gigabit media-independent interface (HSGMII) is functionally similar to the SGMII but supports link speeds of up to 2.5 Gbit/s.Quad serial gigabit media-independent interface
The quad serial gigabit media-independent interface (QSGMII) is a method of combining four SGMII lines into a 5 Gbit/s interface. QSGMII, like SGMII, uses low-voltage differential signaling (LVDS) for the TX and RX data, and a single LVDS clock signal. QSGMII uses significantly fewer signal lines than four separate SGMII connections.10 gigabit media-independent interface
10 gigabit media-independent interface (XGMII) is a standard defined inSee also
* Attachment Unit Interface (AUI) * G.hn, an ITU-T recommendation that uses the term MII to refer to the interface between the data link layer and theReferences
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