List Of Discontinued X86 Instructions

Instructions that have at some point been present as documented instructions in one or more x86 processors, but where the processor series containing the instructions are discontinued or superseded, with no known plans to reintroduce the instructions.

Intel instructions

i386 instructions

These instructions are only present in the x86 operation mode of early Intel Itanium processors with hardware support for x86. This support was added in "Merced" and removed in "Montecito", replaced with software emulation.

MPX instructions

These instructions were introduced in 6th generation Intel Core "Skylake" CPUs. The last CPU generation to support them was the 9th generation Core "Coffee Lake" CPUs.

Intel MPX adds 4 new registers, BND0 to BND3, that each contains a pair of addresses. MPX also defines a bounds-table as a 2-level directory/table data structure in memory that contains sets of upper/lower bounds.

Hardware Lock Elision

The Hardware Lock Elision feature of Intel TSX is marked in the Intel SDM as removed from 2019 onwards. This feature took the form of two instruction prefixes, XACQUIRE and XRELEASE, that could be attached to memory atomics/stores to elide the memory locking that they represent.

Xeon Phi "Knights Corner" instructions

The first generation Xeon Phi processors, codenamed "Knights Corner" (KNC), supported a large number of instructions that are not seen in any later x86 processor. An instruction reference is available - the instructions/opcodes unique to KNC are the ones with VEX and MVEX prefixes (except for the KMOV, KNOT and KORTEST instructions - these are kept with the same opcodes and function in AVX-512, but with an added "W" appended to their instruction names).

Most of these KNC-unique instructions are similar but not identical to instructions in

AVX-512 - later Xeon Phi processors replaced these instructions with AVX-512.

Xeon Phi "Knights Landing" and "Knights Mill" instructions

Some of the AVX-512 instructions in the Xeon Phi "Knights Landing" and later models belong to the AVX-512 subsets "AVX512ER", "AVX512_4FMAPS", "AVX512PF" and "AVX512_4VNNIW", all of which are unique to the Xeon Phi series of processors.

The ER and 4FMAPS instructions are floating-point arithmetic instructions that all follow a given pattern where:
* EVEX.W is used to specify floating-point format (0=FP32, 1=FP64)
* The bottom opcode bit is used to select between packed and scalar operation (0: packed, 1:scalar)
* For a given operation, all the scalar/packed variants belong to the same AVX-512 subset.
* The instructions all support result masking by opmask registers. The AVX512ER instructions also all support broadcast of memory operands.
* The only supported vector width is 512 bits.

AMD instructions

Am386 SMM instructions

A handful of instructions to support System Management Mode were introduced in the Am386SXLV and Am386DXLV processors. They were also present in the later Am486SXLV and Am486DXLV processors.

The SMM functionality of these processors was implemented using Intel ICE microcode without a valid license, resulting in a lawsuit that AMD lost in 1994. As a result of this loss, the ICE microcode was removed from all later AMD CPUs, and the SMM instructions removed with it.

These SMM instructions were also present on the IBM 386SLC and its derivatives (albeit with the LOADALL-like SMM return opcode 0F 07 named "ICERET").

3DNow! instructions

The 3DNow! instruction set extension was introduced in the AMD K6-2, mainly adding support for floating-point SIMD instructions using the MMX registers (two FP32 components in a 64-bit vector). The instructions were mainly promoted by AMD, but were supported on some non-AMD CPUs as well. The processors supporting 3DNow! were:
* AMD K6-2, K6-III, and all processors based on the K7, K8 and K10 microarchitectures. (Later AMD microarchitectures such as Bulldozer, Bobcat and Zen do not support 3DNow!)
* IDT WinChip 2 and 3
* VIA Cyrix III, and the "Samuel" and "Ezra" revisions of VIA C3. (Later VIA CPUs, from C3 "Nehemiah" onwards, dropped 3DNow! in favor of SSE.)
* National Semiconductor Geode GX2; AMD Geode GX and LX.

3DNow! also introduced a couple of prefetch instructions: PREFETCH m8 (opcode 0F 0D /0) and PREFETCHW m8 (opcode 0F 0D /1). These instructions, unlike the rest of 3DNow!, are not discontinued but continue to be supported on modern AMD CPUs. The PREFETCHW instruction is also supported on Intel CPUs starting with 65 nm Pentium 4, albeit executed as NOP until Broadwell.

3DNow+ instructions added with

Athlon and K6-2+

3DNow! instructions specific to

Geode GX and LX

SSE5 derived instructions

SSE5 was a proposed SSE extension by AMD. The bundle did not include the full set of Intel's SSE4 instructions, making it a competitor to SSE4 rather than a successor. AMD chose not to implement SSE5 as originally proposed, however, derived SSE extensions were introduced.

XOP

Introduced with the bulldozer processor core, removed again from Zen (microarchitecture) onward.

A revision of most of the SSE5 instruction set

FMA4

Supported in AMD processors starting with the Bulldozer architecture, removed in Zen. Not supported by any intel chip as of 2017.

Fused multiply-add with four operands. FMA4 was realized in hardware before FMA3.

AMD Trailing Bit Manipulation Instructions

AMD introduced TBM together with BMI1 in its Piledriver line of processors; later AMD Jaguar and Zen-based processors do not support TBM. No Intel processors (as of 2020) support TBM.

Instructions from other vendors

Instructions specific to NEC V-series processors

These instructions are specific to the NEC V20/V30 CPUs and their successors, and do not appear in any non-NEC CPUs. Many of their opcodes have been reassigned to other instructions in later non-NEC CPUs.

Instructions specific to

Cyrix and Geode CPUs

These instructions are present in Cyrix CPUs as well as NatSemi/AMD Geode CPUs derived from Cyrix microarchitectures (Geode GX and LX, but not NX). They are also present in Cyrix manufacturing partner CPUs from IBM, ST and TI, as well as a few SoCs such as STPC ATLAS and ZFMicro ZFx86. Many of these opcodes have been reassigned to other instructions in later non-Cyrix CPUs.

Cyrix EMMI instructions

These instructions were introduced in the Cyrix 6x86MX and MII processors, and were also present in the MediaGXm and Geode GX1 processors. (In later non-Cyrix processors, all of their opcodes have been used for SSE instructions.)

These instructions are integer SIMD instructions acting on 64-bit vectors in MMX registers or memory. Each instruction takes two explicit operands, where the first one is an MMX register operand and the second one is either a memory operand or a second MMX register. In addition, several of the instructions take an implied operand, which is an MMX register implied from the first operand as follows:

In the instruction descriptions in the below table, arg1 and arg2 refer to the two explicit operands of the instruction, and imp to the implied operand. For PDISTIB, PMACHRIW and the PMV* instructions, the second explicit operand is required to be a memory operand.

Instructions specific to

Chips and Technologies CPUs

The C&T F8680 PC/Chip is a system-on-a-chip featuring an 80186-compatible CPU core, with a few additional instructions to support the F8680-specific "SuperState R" supervisor/system-management feature. Some of the added instructions for "SuperState R" are:

C&T also developed a 386-compatible processor known as the Super386. This processor supports, in addition to the basic Intel 386 instruction set, a number of instructions to support the Super386-specific "SuperState V" system-management feature. The added instructions for "SuperState V" are:Microprocessor Report
System Management Mode Explained
(vol 6, no. 8, june 17, 1992) - includes a listing of the AMD/Cyrix SMM opcodes and the C&T Super386 "SuperState V" opcodes.

Instructions specific to

ALi/ DM&P M6117 MCUs

The M6117 series of embedded microcontrollers feature a 386SX-class CPU core with a few M6117-specific additions to the Intel 386 instruction set. The ones documented for DM&P M1167D are:DM&P
M6117D : System on a chip
pages 31,34,68
Archived
on Jul 20,2006.

Instructions present in specific

80387 clones

Several 80387-class floating-point coprocessors provided extra instructions in addition to the standard 80387 ones - none of these are supported in later processors:

See also

* x86 instruction listings

References

{{x86 assembly topics

Instruction set listings