The
Sempron
Sempron has been the marketing name used by AMD for several different budget desktop CPUs, using several different technologies and CPU socket formats. The Sempron replaced the AMD Duron processor and competed against Intel's Celeron series of pr ...
is a name used for AMD's low-end CPUs, replacing the
Duron
Duron is a line of budget x86-compatible microprocessors manufactured by AMD. Released on June 19, 2000 as a lower-cost offering to complement AMD's then mainstream performance Athlon processor line, it also competed with rival chipmaker Inte ...
processor. The name was introduced in 2004, and processors with this name continued to be available for the FM2/FM2+ socket in 2015.
Features overview
CPU features table
Desktop processors
Sempron
"Thoroughbred-B" (
Socket A
Socket A (also known as Socket 462) is a zero insertion force pin grid array (PGA) CPU socket used for AMD processors ranging from the Athlon Thunderbird to the Athlon XP/MP 3200+, and AMD budget processors including the Duron and Sempron. Soc ...
, 130 nm, Model 8)
* All models support: ''
MMX,
SSE,
Enhanced 3DNow!''
"Thorton" (
Socket A
Socket A (also known as Socket 462) is a zero insertion force pin grid array (PGA) CPU socket used for AMD processors ranging from the Athlon Thunderbird to the Athlon XP/MP 3200+, and AMD budget processors including the Duron and Sempron. Soc ...
, 130 nm, Model 10)
* All models support: ''
MMX,
SSE,
Enhanced 3DNow!''
"Barton" (
Socket A
Socket A (also known as Socket 462) is a zero insertion force pin grid array (PGA) CPU socket used for AMD processors ranging from the Athlon Thunderbird to the Athlon XP/MP 3200+, and AMD budget processors including the Duron and Sempron. Soc ...
, 130 nm, Model 10)
* All models support: ''
MMX, Extended MMX,
SSE,
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
Enhanced 3DNow!''
"Paris" (
Socket 754
Socket 754 is a CPU socket originally developed by AMD to supersede its Athlon XP platform (Socket 462, also referred to as Socket A). Socket 754 was the first socket developed by AMD to support their new consumer version of the 64 bit micropro ...
, CG, 130 nm)
* All models support: ''
MMX,
SSE,
SSE2,
Enhanced 3DNow!,
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit i ...
''
"Palermo" (
Socket 754
Socket 754 is a CPU socket originally developed by AMD to supersede its Athlon XP platform (Socket 462, also referred to as Socket A). Socket 754 was the first socket developed by AMD to support their new consumer version of the 64 bit micropro ...
, D0, E3 & E6, 90 nm)
* All models support: ''
MMX,
SSE,
SSE2,
Enhanced 3DNow!,
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit i ...
''
* ''
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
'' supported by: all models with an OPN ending in BO and BX
* ''
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
'' supported by: all models with an OPN ending in BX and CV
* ''
Cool'n'Quiet
AMD Cool'n'Quiet is a CPU dynamic frequency scaling and power saving technology introduced by AMD with its Athlon XP processor line. It works by reducing the processor's clock rate and voltage when the processor is idle. The aim of this techn ...
'' supported by: 3000+ and higher models
"Palermo" (
Socket 939
Socket 939 is a CPU socket released by AMD in June 2004 to supersede the previous Socket 754 for Athlon 64 processors. Socket 939 was succeeded by Socket AM2 in May 2006. It is the second socket designed for AMD's AMD64 range of processors.
Av ...
, E3 & E6, 90 nm)
* All models support: ''
MMX,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
Enhanced 3DNow!,
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit i ...
''
* ''
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
'' supported by: all models with an OPN ending in BW
"Manila" ( Socket AM2, F2, 90 nm)
* All models support: ''
MMX,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
Enhanced 3DNow!,
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit i ...
,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
''
* ''
Cool'n'Quiet
AMD Cool'n'Quiet is a CPU dynamic frequency scaling and power saving technology introduced by AMD with its Athlon XP processor line. It works by reducing the processor's clock rate and voltage when the processor is idle. The aim of this techn ...
'' supported by: 3200+ and higher models
"Manila" ( Socket AM2, Energy Efficient Small Form Factor, F2, 90 nm)
* All models support: ''
MMX,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
Enhanced 3DNow!,
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit i ...
,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
''
* ''
Cool'n'Quiet
AMD Cool'n'Quiet is a CPU dynamic frequency scaling and power saving technology introduced by AMD with its Athlon XP processor line. It works by reducing the processor's clock rate and voltage when the processor is idle. The aim of this techn ...
'' supported by: 3200+ and higher models
"Sparta" ( Socket AM2, Energy Efficient, G1 & G2, 65 nm)
* All models support: ''
MMX,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
Enhanced 3DNow!,
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit i ...
,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
'', ''
Cool'n'Quiet
AMD Cool'n'Quiet is a CPU dynamic frequency scaling and power saving technology introduced by AMD with its Athlon XP processor line. It works by reducing the processor's clock rate and voltage when the processor is idle. The aim of this techn ...
''
"Brisbane" ( Socket AM2, Dual-core, G1 & G2, 65 nm)
* All models support: ''
MMX,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
Enhanced 3DNow!,
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit i ...
,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
'', ''
Cool'n'Quiet
AMD Cool'n'Quiet is a CPU dynamic frequency scaling and power saving technology introduced by AMD with its Athlon XP processor line. It works by reducing the processor's clock rate and voltage when the processor is idle. The aim of this techn ...
''
"Sargas" (
Socket AM3
Socket AM3 is a CPU socket for AMD processors. AM3 was launched on February 9, 2009 as the successor to Socket AM2+, alongside the initial grouping of Phenom II processors designed for it. The sole principal change from AM2+ to AM3 is support for ...
, Single-core, C2 & C3, 45 nm)
* Chip harvests from Regor with one core disabled
* All models support: ''
MMX,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSE4a,
ABM,
Enhanced 3DNow!,
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit i ...
,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
Cool'n'Quiet
AMD Cool'n'Quiet is a CPU dynamic frequency scaling and power saving technology introduced by AMD with its Athlon XP processor line. It works by reducing the processor's clock rate and voltage when the processor is idle. The aim of this techn ...
,
AMD-V''
"Regor" (Socket AM3, Dual-core, C3, 45 nm)
* All models support: ''
MMX,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSE4a,
ABM,
Enhanced 3DNow!,
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit i ...
,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
Cool'n'Quiet
AMD Cool'n'Quiet is a CPU dynamic frequency scaling and power saving technology introduced by AMD with its Athlon XP processor line. It works by reducing the processor's clock rate and voltage when the processor is idle. The aim of this techn ...
,
AMD-V''
FM2/FM2+ Semprons ( Socket FM2, Dual-core, 32 nm)
*Piledriver microarchitecture, Trinity/Richland core
* All models support: ''
MMX,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3
Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.
History
SSSE3 was first introduced with Intel processors based on the Core microarchitectu ...
,
SSE4a,
SSE4.1
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; mor ...
,
SSE4.2
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core (microarchitecture), Core microarchitecture and AMD K10, AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vag ...
,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
AMD-V,
AES,
CLMUL Carry-less Multiplication (CLMUL) is an extension to the x86 instruction set used by microprocessors from Intel and AMD which was proposed by Intel in March 2008 and made available in the Intel Westmere processors announced in early 2010. Mathema ...
,
AVX 1.1,
XOP,
FMA3
The FMA instruction set is an extension to the 128 and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations."FMA3 and FMA4 are not instruction sets, they are i ...
,
FMA4,
F16C
The F16C (previously/informally known as CVT16) instruction set is an x86 instruction set architecture extension which provides support for converting between half-precision and standard IEEE single-precision floating-point formats.
History
T ...
,
ABM,
BMI1
Polycomb complex protein BMI-1 also known as polycomb group RING finger protein 4 (PCGF4) or RING finger protein 51 (RNF51) is a protein that in humans is encoded by the ''BMI1'' gene (B cell-specific Moloney murine leukemia virus integration ...
,
TBM''
"Kabini" (
Socket AM1
Socket FS1b (rebranded as Socket AM1 ) is a socket designed by AMD, launched in April 2014 for desktop SoCs in the value segment. Socket AM1 is intended for a class of CPUs that contain both an integrated GPU and a chipset, essentially forming a ...
, Dual-core or Quad-core, 28 nm)
* All models support: ''
MMX,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSSE3
Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.
History
SSSE3 was first introduced with Intel processors based on the Core microarchitectu ...
,
SSE4a,
SSE4.1
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; mor ...
,
SSE4.2
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core (microarchitecture), Core microarchitecture and AMD K10, AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vag ...
,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
AVX,
F16C
The F16C (previously/informally known as CVT16) instruction set is an x86 instruction set architecture extension which provides support for converting between half-precision and standard IEEE single-precision floating-point formats.
History
T ...
,
CLMUL Carry-less Multiplication (CLMUL) is an extension to the x86 instruction set used by microprocessors from Intel and AMD which was proposed by Intel in March 2008 and made available in the Intel Westmere processors announced in early 2010. Mathema ...
,
AES, MOVBE (Move Big-Endian instruction),
ABM,
BMI1
Polycomb complex protein BMI-1 also known as polycomb group RING finger protein 4 (PCGF4) or RING finger protein 51 (RNF51) is a protein that in humans is encoded by the ''BMI1'' gene (B cell-specific Moloney murine leukemia virus integration ...
,
AMD-V''
Mobile processors
Mobile Sempron
"Dublin" (
Socket 754
Socket 754 is a CPU socket originally developed by AMD to supersede its Athlon XP platform (Socket 462, also referred to as Socket A). Socket 754 was the first socket developed by AMD to support their new consumer version of the 64 bit micropro ...
, CG, 130 nm, Desktop replacement)
* All models support: ''
MMX,
SSE,
SSE2,
Enhanced 3DNow!,
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit i ...
''
"Dublin" (
Socket 754
Socket 754 is a CPU socket originally developed by AMD to supersede its Athlon XP platform (Socket 462, also referred to as Socket A). Socket 754 was the first socket developed by AMD to support their new consumer version of the 64 bit micropro ...
, CG, 130 nm, Low power)
* All models support: ''
MMX,
SSE,
SSE2,
Enhanced 3DNow!,
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit i ...
''
"Georgetown" (
Socket 754
Socket 754 is a CPU socket originally developed by AMD to supersede its Athlon XP platform (Socket 462, also referred to as Socket A). Socket 754 was the first socket developed by AMD to support their new consumer version of the 64 bit micropro ...
, D0, 90 nm, Desktop replacement)
* All models support: ''
MMX,
SSE,
SSE2,
Enhanced 3DNow!,
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit i ...
''
"Sonora" (
Socket 754
Socket 754 is a CPU socket originally developed by AMD to supersede its Athlon XP platform (Socket 462, also referred to as Socket A). Socket 754 was the first socket developed by AMD to support their new consumer version of the 64 bit micropro ...
, D0, 90 nm, Low power)
* All models support: ''
MMX,
SSE,
SSE2,
Enhanced 3DNow!,
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit i ...
''
"Albany" (
Socket 754
Socket 754 is a CPU socket originally developed by AMD to supersede its Athlon XP platform (Socket 462, also referred to as Socket A). Socket 754 was the first socket developed by AMD to support their new consumer version of the 64 bit micropro ...
, E6, 90 nm, Desktop replacement)
* All models support: ''
MMX,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
Enhanced 3DNow!,
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit i ...
''
"Roma" (
Socket 754
Socket 754 is a CPU socket originally developed by AMD to supersede its Athlon XP platform (Socket 462, also referred to as Socket A). Socket 754 was the first socket developed by AMD to support their new consumer version of the 64 bit micropro ...
, E6, 90 nm, Low power)
* All models support: ''
MMX,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
Enhanced 3DNow!,
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit i ...
''
"Keene" (
Socket S1
Socket S1 is the CPU socket type used by AMD for their Turion 64, Athlon 64 Mobile, Phenom II Mobile and later Sempron processors, which debuted with the dual-core Turion 64 X2 CPUs on May 17, 2006.
Technical specifications
Socket S1 is a 638 ...
, F2, 90 nm, Low power)
* All models support: ''
MMX,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
Enhanced 3DNow!,
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit i ...
,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
PowerNow!
__NOTOC__
AMD PowerNow! is AMD's dynamic frequency scaling and power saving technology for laptop processors. The CPU's clock speed and VCore are automatically decreased when the computer is under low load or idle, to save battery power, reduc ...
''
"Sherman" (
Socket S1
Socket S1 is the CPU socket type used by AMD for their Turion 64, Athlon 64 Mobile, Phenom II Mobile and later Sempron processors, which debuted with the dual-core Turion 64 X2 CPUs on May 17, 2006.
Technical specifications
Socket S1 is a 638 ...
, G1 & G2, 65 nm, Low power)
* All models support: ''
MMX,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
Enhanced 3DNow!,
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit i ...
,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
''
"Sable" (
65 nm
The 65 nm process is an advanced lithographic node used in volume CMOS ( MOSFET) semiconductor fabrication. Printed linewidths (i.e. transistor gate lengths) can reach as low as 25 nm on a nominally 65 nm process, while the pitc ...
)
* All models support: ''
MMX,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
Enhanced 3DNow!,
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit i ...
,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
PowerNow!
__NOTOC__
AMD PowerNow! is AMD's dynamic frequency scaling and power saving technology for laptop processors. The CPU's clock speed and VCore are automatically decreased when the computer is under low load or idle, to save battery power, reduc ...
''
"Huron" (
65 nm
The 65 nm process is an advanced lithographic node used in volume CMOS ( MOSFET) semiconductor fabrication. Printed linewidths (i.e. transistor gate lengths) can reach as low as 25 nm on a nominally 65 nm process, while the pitc ...
, Low power)
* All models support: ''
MMX,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
Enhanced 3DNow!,
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit i ...
,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
PowerNow!
__NOTOC__
AMD PowerNow! is AMD's dynamic frequency scaling and power saving technology for laptop processors. The CPU's clock speed and VCore are automatically decreased when the computer is under low load or idle, to save battery power, reduc ...
''
"Caspian" (
45 nm
Per the International Technology Roadmap for Semiconductors, the 45 nm process is a MOSFET technology node referring to the average half-pitch of a memory cell manufactured at around the 2007–2008 time frame.
Matsushita and Intel started mass ...
)
* All models support: ''
MMX,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSE4a,
Enhanced 3DNow!,
NX bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit i ...
,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
PowerNow!
__NOTOC__
AMD PowerNow! is AMD's dynamic frequency scaling and power saving technology for laptop processors. The CPU's clock speed and VCore are automatically decreased when the computer is under low load or idle, to save battery power, reduc ...
,
AMD-V''
Notes
See also
*
Sempron
Sempron has been the marketing name used by AMD for several different budget desktop CPUs, using several different technologies and CPU socket formats. The Sempron replaced the AMD Duron processor and competed against Intel's Celeron series of pr ...
*
List of AMD Athlon XP processors
The Athlon XP microprocessor from AMD is a seventh-generation 32-bit CPU targeted at the consumer market.
Features overview
Desktop CPU Athlon XP "Palomino" (Model 6, 180 nm)
* CPU-ID: 6-6-0, 6-6-1, 6-6-2
* All models support: ''MMX, SSE, ...
*
List of AMD Athlon 64 processors
The Athlon 64 microprocessor from Advanced Micro Devices (AMD) is an eighth-generation central processing unit (CPU). Athlon 64 is targeted at the consumer market.
Features overview
CPU features table
Single-core desktop processors
Athlon 6 ...
*
List of AMD Turion processors
Turion 64 is the name of a family of CPUs designed by AMD for the mobile computing market.
Features overview
CPU features table
Single-core mobile processors
Turion 64
"Lancaster" (90 nm)
* All models support: ''MMX, SSE, SSE2, SSE3, Enh ...
*
Table of AMD processors
References
See also
* List of AMD microprocessors
* List of AMD CPU microarchitectures
* List of AMD mobile microprocessors
* List of AMD Athlon microprocessors
* List of AMD Athlon XP microprocessors
* List of AMD Athlon 64 microprocesso ...
References
External links
* https://web.archive.org/web/20080103192839/http://products.amd.com/en-us/NotebookCPUFilter.aspx
* https://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_609,00.html?redir=CPT301 (AMD's pricing page)
* https://web.archive.org/web/20050812003814/http://h18000.www1.hp.com/products/quickspecs/12105_na/12105_na.HTML (includes information on Socket 939 Semprons)
* https://web.archive.org/web/20051026082412/http://www.xbitlabs.com/articles/cpu/display/sempron-3000_2.html (info on Socket 939 3000+)
* https://web.archive.org/web/20051026081750/http://www.xbitlabs.com/articles/cpu/display/sempron-3000_4.html (more info on Socket 939 Semprons)
* http://www.digital-daily.com/cpu/sempron_3000_939/ (more recent info about Socket 939 Semprons)
{{AMD processors
*Sempron
AMD Sempron