Hybrid Memory Cube (HMC) is a high-performance computer
random-access memory
Random-access memory (RAM; ) is a form of computer memory that can be read and changed in any order, typically used to store working data and machine code. A random-access memory device allows data items to be read or written in almost the ...
(RAM) interface for
through-silicon via
In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high-performance interconnect techniques used as an alternative ...
s (TSV)-based stacked DRAM memory competing with the incompatible rival interface
High Bandwidth Memory
High Bandwidth Memory (HBM) is a high-speed computer memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM) initially from Samsung, AMD and SK Hynix. It is used in conjunction with high-performance graphics accelerator ...
(HBM).
Overview
Hybrid Memory Cube was co-developed by
Samsung Electronics
Samsung Electronics Co., Ltd. (, sometimes shortened to SEC and stylized as SΛMSUNG) is a South Korean multinational electronics corporation headquartered in Yeongtong-gu, Suwon, South Korea. It is the pinnacle of the Samsung chaebol, a ...
and
Micron Technology in 2011, and announced by Micron in September 2011.
[Micron Reinvents DRAM Memory](_blank)
Linley Group, Jag Bolaria, 12 September 2011 It promised a 15 times speed improvement over
DDR3
Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth (" double data rate") interface, and has been in use since 2007. It is the higher-spee ...
.
The Hybrid Memory Cube Consortium (HMCC) is backed by several major technology companies including
Samsung
The Samsung Group (or simply Samsung) ( ko, 삼성 ) is a South Korean multinational manufacturing conglomerate headquartered in Samsung Town, Seoul, South Korea. It comprises numerous affiliated businesses, most of them united under the ...
,
Micron Technology,
Open-Silicon,
ARM
In human anatomy, the arm refers to the upper limb in common usage, although academically the term specifically means the upper arm between the glenohumeral joint (shoulder joint) and the elbow joint. The distal part of the upper limb between th ...
,
HP (since withdrawn),
Microsoft
Microsoft Corporation is an American multinational technology corporation producing computer software, consumer electronics, personal computers, and related services headquartered at the Microsoft Redmond campus located in Redmond, Washin ...
(since withdrawn),
Altera
Altera Corporation was a manufacturer of programmable logic devices (PLDs) headquartered in San Jose, California. It was founded in 1983 and acquired by Intel in 2015.
The main product lines from Altera were the flagship Stratix series, mid-ran ...
(acquired by Intel in late 2015), and
Xilinx
Xilinx, Inc. ( ) was an American technology and semiconductor company that primarily supplied programmable logic devices. The company was known for inventing the first commercially viable field-programmable gate array (FPGA) and creating the ...
. Micron, while continuing to support HMCC, is discontinuing the HMC product in 2018 when it failed to achieve market adoption.
HMC combines
through-silicon via
In electronic engineering, a through-silicon via (TSV) or through-chip via is a vertical electrical connection (via) that passes completely through a silicon wafer or die. TSVs are high-performance interconnect techniques used as an alternative ...
s (TSV) and
microbump
In integrated circuit packaging, a solder ball, also a solder bump (ofter referred to simply as "ball" or "bumps") is a ball of solder that provides the contact between the chip package and the printed circuit board, as well as between stacked ...
s to connect multiple (currently 4 to 8)
dies of memory cell arrays on top of each other.
The memory controller is integrated as a separate die.
HMC uses standard DRAM cells but it has more data banks than classic
DRAM memory of the same size. The HMC interface is incompatible with current DDR''n'' (
DDR2 or
DDR3
Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth (" double data rate") interface, and has been in use since 2007. It is the higher-spee ...
) and competing
High Bandwidth Memory
High Bandwidth Memory (HBM) is a high-speed computer memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM) initially from Samsung, AMD and SK Hynix. It is used in conjunction with high-performance graphics accelerator ...
implementations.
[Memory for Exascale and ... Micron's new memory component is called HMC: Hybrid Memory Cube](_blank)
by Dave Resnick (Sandia National Laboratories) // 2011 Workshop on Architectures I: Exascale and Beyond, 8 July 2011
HMC technology won the Best New Technology award from The Linley Group (publisher of ''Microprocessor Report'' magazine) in 2011.
The first public specification, HMC 1.0, was published in April 2013. According to it, the HMC uses 16-lane or 8-lane (half size) full-duplex differential serial links, with each lane having 10, 12.5 or 15
Gbit
The bit is the most basic unit of information in computing and digital communications. The name is a portmanteau of binary digit. The bit represents a logical state with one of two possible values. These values are most commonly represented ...
/s
SerDes
{{Use American English, date = March 2019
A Serializer/Deserializer (SerDes) is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and paral ...
. Each HMC package is named a ''cube'', and they can be chained in a network of up to 8 cubes with cube-to-cube links and some cubes using their links as pass-through links. A typical cube package with 4 links has 896 BGA pins and a size of 31×31×3.8 millimeters.
The typical raw
bandwidth
Bandwidth commonly refers to:
* Bandwidth (signal processing) or ''analog bandwidth'', ''frequency bandwidth'', or ''radio bandwidth'', a measure of the width of a frequency range
* Bandwidth (computing), the rate of data transfer, bit rate or thr ...
of a single 16-lane link with 10 Gbit/s signalling implies a total bandwidth of all 16 lanes of 40
GB/s (20 GB/s transmit and 20 GB/s receive); cubes with 4 and 8 links are planned, though the HMC 1.0 spec limits link speed to 10 Gbit/s in the 8-link case. Therefore, a 4-link cube can reach 240
GB/s
In telecommunications, data-transfer rate is the average number of bits (bitrate), characters or symbols (baudrate), or data blocks per unit time passing through a communication link in a data-transmission system. Common data rate units are multi ...
memory bandwidth (120 GB/s each direction using 15 Gbit/s SerDes), while an 8-link cube can reach 320 GB/s bandwidth (160 GB/s each direction using 10 Gbit/s SerDes). Effective memory bandwidth utilization varies from 33% to 50% for smallest packets of 32 bytes; and from 45% to 85% for 128 byte packets.
[Hybrid Memory Cube (HMC), J. Thomas Pawlowski (Micron) // HotChips 23]
As reported at the HotChips 23 conference in 2011, the first generation of HMC demonstration cubes with four 50 nm DRAM memory dies and one 90 nm logic die with total capacity of 512
MB and size 27×27 mm had power consumption of 11 W and was powered with 1.2 V.
Engineering samples of second generation HMC memory chips were shipped in September 2013 by Micron.
Samples of 2 GB HMC (stack of 4 memory dies, each of 4 Gbit) are packed in a 31×31 mm package and have 4 HMC links. Other samples from 2013 have only two HMC links and a smaller package: 16×19.5 mm.
The second version of the HMC specification was published on 18 November 2014 by HMCC. HMC2 offers a variety of SerDes rates ranging from 12.5 Gbit/s to 30 Gbit/s, yielding an aggregate link bandwidth of 480
GB/s
In telecommunications, data-transfer rate is the average number of bits (bitrate), characters or symbols (baudrate), or data blocks per unit time passing through a communication link in a data-transmission system. Common data rate units are multi ...
(240 GB/s each direction), though promising only a total DRAM bandwidth of 320 GB/sec. A package may have either 2 or 4 links (down from the 4 or 8 in HMC1), and a quarter-width option is added using 4 lanes.
The first processor to use HMCs was the
Fujitsu SPARC64 XIfx, which is used in the
Fujitsu PRIMEHPC FX100 supercomputer introduced in 2015.
JEDEC
The JEDEC Solid State Technology Association is an independent semiconductor engineering trade organization and standardization body headquartered in Arlington County, Virginia, United States.
JEDEC has over 300 members, including some of the w ...
's Wide I/O and Wide I/O 2 are seen as the mobile computing counterparts to the desktop/server-oriented HMC in that both involve 3D die stacks.
In August 2018, Micron announced a move away from HMC to pursue competing high-performance memory technologies such as
GDDR6
Graphics Double Data Rate 6 Synchronous Dynamic Random-Access Memory (GDDR6 SDRAM) is a type of synchronous graphics random-access memory (SGRAM) with a high bandwidth, " double data rate" interface, designed for use in graphics cards, game cons ...
and
HBM.
See also
*
MCDRAM
Multi-Channel DRAM or MCDRAM (pronounced ''em cee dee ram'') is a 3D-stacked DRAM that is used in the Intel Xeon Phi processor codenamed Knights Landing. It is a version of Hybrid Memory Cube developed in partnership with Micron Technology, and ...
*
Memristor
A memristor (; a portmanteau of ''memory resistor'') is a non-linear two-terminal electrical component relating electric charge and magnetic flux linkage. It was described and named in 1971 by Leon Chua, completing a theoretical quartet of fu ...
*
Stacked DRAM
*
Chip stack multi-chip modules
*
High Bandwidth Memory
High Bandwidth Memory (HBM) is a high-speed computer memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM) initially from Samsung, AMD and SK Hynix. It is used in conjunction with high-performance graphics accelerator ...
(HBM), developed by
AMD
Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. While it initially manufactur ...
and
Hynix
SK hynix Inc. is a South Korean supplier of dynamic random-access memory (DRAM) chips and flash memory chips. Hynix is the world's second-largest memory chipmaker (after Samsung Electronics) and the world's third-largest semiconductor company. ...
, used in AMD's
Fiji, and
Nvidia
Nvidia CorporationOfficially written as NVIDIA and stylized in its logo as VIDIA with the lowercase "n" the same height as the uppercase "VIDIA"; formerly stylized as VIDIA with a large italicized lowercase "n" on products from the mid 1990s to ...
's
Pascal
References
External links
*
HMC 1.0 SpecificationHMC 2.0 Specification download form*{{youtube, h2swEqw6pbg, Revolutionary Advancements in Memory Performance
Hybrid Memory Cube (HMC) J. Thomas Pawlowski (Micron) // HotChips 23, 2011
Stacking Stairs Against the Memory Wallby Nicole Hemsoth // HPC Wire, 2 April 2013
Computer memory