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The media-independent interface (MII) was originally defined as a standard interface to connect a
Fast Ethernet In computer networking, Fast Ethernet physical layers carry traffic at the nominal rate of 100 Mbit/s. The prior Ethernet speed was 10 Mbit/s. Of the Fast Ethernet physical layers, 100BASE-TX is by far the most common. Fast Ethern ...
(i.e., )
media access control In IEEE 802 LAN/MAN standards, the medium access control (MAC, also called media access control) sublayer is the layer that controls the hardware responsible for interaction with the wired, optical or wireless transmission medium. The MAC sublay ...
(MAC) block to a PHY chip. The MII is standardized by
IEEE 802.3u In computer networking, Fast Ethernet physical layers carry traffic at the nominal rate of 100 Mbit/s. The prior Ethernet speed was 10 Mbit/s. Of the Fast Ethernet physical layers, 100BASE-TX is by far the most common. Fast Ethern ...
and connects different types of PHYs to MACs. Being ''media independent'' means that different types of PHY devices for connecting to different media (i.e.
twisted pair Twisted pair cabling is a type of wiring used for communications in which two conductors of a single circuit are twisted together for the purposes of improving electromagnetic compatibility. Compared to a single conductor or an untwisted ba ...
,
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, etc.) can be used without redesigning or replacing the MAC hardware. Thus any MAC may be used with any PHY, independent of the network signal transmission media. The MII can be used to connect a MAC to an external PHY using a pluggable connector, or directly to a PHY chip on the same PCB. On a PC the CNR connector Type B carries MII signals. Network data on the interface is framed using the IEEE
Ethernet Ethernet () is a family of wired computer networking technologies commonly used in local area networks (LAN), metropolitan area networks (MAN) and wide area networks (WAN). It was commercially introduced in 1980 and first standardized in 1 ...
standard. As such it consists of a preamble, start frame delimiter, Ethernet headers, protocol-specific data and a cyclic redundancy check (CRC). The original MII transfers network data using 4-bit nibbles in each direction (4 transmit data bits, 4 receive data bits). The data is clocked at 25 MHz to achieve 100 Mbit/s throughput. The original MII design has been extended to support reduced signals and increased speeds. Current variants include: * Reduced media-independent interface (RMII) * Gigabit media-independent interface (GMII) * Reduced gigabit media-independent interface (RGMII) * Serial media-independent interface (SMII) * Serial gigabit media-independent interface (serial GMII, SGMII) * High serial gigabit media-independent interface (HSGMII) * Quad serial gigabit media-independent interface (QSGMII) * 10-gigabit media-independent interface (XGMII) The Management Data Input/Output (MDIO) serial bus is a subset of the MII that is used to transfer management information between MAC and PHY. At power up, using autonegotiation, the PHY usually adapts to whatever it is connected to unless settings are altered via the MDIO interface.


Standard MII

The standard MII features a small set of registers: * Basic Mode Configuration (#0) * Status Word (#1) * PHY Identifier (#2, #3) * Auto-Negotiation Advertisement (#4) * Auto-Negotiation Link Partner Base Page Ability (#5) * Auto-Negotiation Expansion (#6) * Auto-Negotiation Next Page Transmit (#7) * Auto-Negotiation Link Partner Received Next Page (#8) * MASTER-SLAVE Control Register (#9) * MASTER-SLAVE Status Register (#10) * PSE Control register (#11) * PSE Status register (#12) * MMD Access Control Register (#13) * MMD Access Address Data Register (#14) Register #15 is reserved; registers #16 through #31 are vendor-specific. The registers are used to configure the device and to query the current operating mode. The MII Status Word is the most useful datum, since it may be used to detect whether an Ethernet NIC is connected to a network. It contains a
bit field A bit field is a data structure that consists of one or more adjacent bits which have been allocated for specific purposes, so that any single bit or group of bits within the structure can be set or inspected. A bit field is most commonly used to ...
with the following information:


Transmitter signals

The transmit clock is a free-running clock generated by the PHY based on the link speed (25 MHz for 100 Mbit/s, 2.5 MHz for 10 Mbit/s). The remaining transmit signals are driven by the MAC synchronously on the rising edge of TX_CLK. This arrangement allows the MAC to operate without having to be aware of the link speed. The transmit enable signal is held high during frame transmission and low when the transmitter is idle. Transmit error may be raised for one or more clock periods during frame transmission to request the PHY to deliberately corrupt the frame in some visible way that precludes it from being received as valid. This may be used to abort a frame when some problem is detected after transmission has already started. The MAC may omit the signal if it has no use for this functionality, in which case the signal should be tied low for the PHY. More recently, raising transmit error ''outside'' frame transmission is used to indicate the transmit data lines are being used for special-purpose signalling. Specifically, the data value 0b0001 (held continuously with TX_EN low and TX_ER high) is used to request an
EEE EEE may refer to: Business * ''Electronic Equipment Engineering'', a defunct American trade magazine * Embrace, extend and extinguish, an anti-competitive Microsoft business strategy * Coca-Cola Hellenic Bottling Company (trades as EEE) * Union of ...
-capable PHY to enter low power mode.


Receiver signals

The first seven receiver signals are entirely analogous to the transmitter signals, except RX_ER is not optional and used to indicate the received signal could not be decoded to valid data. The receive clock is recovered from the incoming signal during frame reception. When no clock can be recovered (i.e. when the medium is silent), the PHY must present a free-running clock as a substitute. The receive data valid signal (RX_DV) is not required to go high immediately when the frame starts, but must do so in time to ensure the "start of frame delimiter" byte is included in the received data. Some of the preamble nibbles may be lost. Similar to transmit, raising RX_ER outside a frame is used for special signalling. For receive, two data values are defined: 0b0001 to indicate the link partner is in EEE low power mode, and 0b1110 for a ''false carrier'' indication. The CRS and COL signals are asynchronous to the receive clock, and are only meaningful in half-duplex mode. Carrier sense is high when transmitting, receiving, or the medium is otherwise sensed as being in use. If a collision is detected, COL also goes high while the collision persists. In addition, the MAC may weakly pull-up the COL signal, allowing the combination of COL high with CRS low (which a PHY will never produce) to serve as indication of an absent/disconnected PHY.


Management signals

MDC and MDIO constitute a synchronous serial data interface similar to
I²C I2C (Inter-Integrated Circuit, ), alternatively known as I2C or IIC, is a synchronous, multi-controller/multi-target (master/slave), packet switched, single-ended, serial communication bus invented in 1982 by Philips Semiconductors. It is wi ...
. As with I²C, the interface is a
multidrop bus A multidrop bus (MDB) is a computer bus in which all components are connected to the electrical circuit. A process of arbitration determines which device sends information at any point. The other devices listen for the data they are intended to re ...
so MDC and MDIO can be shared among multiple PHYs.


Limitations

The interface requires 18 signals, out of which only two (MDIO and MDC) can be shared among multiple PHYs. This presents a problem, especially for multiport devices; for example, an eight-port switch using MII would need 8 × 16 + 2 = 130 signals.


Reduced media-independent interface

Reduced media-independent interface (RMII) is a standard which was developed to reduce the number of signals required to connect a PHY to a MAC. Reducing pin count reduces cost and complexity for network hardware especially in the context of microcontrollers with built-in MAC, FPGAs, multiport switches or repeaters, and PC motherboard chipsets. Four things were changed compared to the MII standard to achieve this. These changes mean that RMII uses about half the number of signals compared to MII. * The two clocks TXCLK and RXCLK are replaced by a single clock. This clock is an input to the PHY rather than an output, which allows the clock signal to be shared among all PHYs in a multiport device, such as a switch. * The clock frequency is doubled from 25 MHz to 50 MHz, while the data paths are narrowed from 4 bits to 2 bits. * RXDV and CRS signals are multiplexed into one signal. * The COL signal is removed. MDC and MDIO can be shared among multiple PHYs. The receiver signals are referenced to the REF_CLK, same as the transmitter signals. This interface requires 9 signals, versus MII's 18. Of those 9, on multiport devices, MDIO, MDC, and REF_CLK may be shared leaving 6 or 7 pins per port. RMII requires a clock where MII requires a clock and data is clocked out two bits at a time vs 4 bits at a time for MII or 1 bit at a time for SNI (10 Mbit/s only). Data is sampled on the rising edge only (i.e. it is ''not'' double-pumped). The REF_CLK operates at 50 MHz in both mode and mode. The transmitting side (PHY or MAC) must keep all signals valid for 10 clock cycles in mode. The receiver (PHY or MAC) samples the input signals only every ten cycles in mode.


Limitations

There is no signal which defines whether the interface is in full or half duplex mode, but both the MAC and the PHY need to agree. This must instead be communicated over the serial MDIO/MDC interface. There is also no signal which defines whether the interface is in 10 or 100 Mbit/s mode, so this must also be handled using the MDIO/MDC interface. Version 1.2 of the RMII Consortium specification states that its MDIO/MDC interface is identical to that specified for MII in IEEE 802.3u. Current revisions of IEEE 802.3 specify a standard MDIO/MDC mechanism for negotiating and configuring the link's speed and duplex mode, but it is possible that older PHY devices might have been designed against obsolete versions of the standard, and may therefore use proprietary methods to set speed and duplex. The lack of the RX_ER signal which is not connected on some MACs (such as multiport switches) is dealt with by data replacement on some PHYs to invalidate the CRC. The missing COL signal is derived from AND-ing together the TX_EN and the decoded CRS signal from the CRS_DV line in half duplex mode. This means a slight modification of the definition of CRS: On MII, CRS is asserted for both Rx and Tx frames; on RMII only for Rx frames. This has the consequence that on RMII the two error conditions ''no carrier'' and ''lost carrier'' cannot be detected, and it is difficult or impossible to support shared media such as 10BASE2 or
10BASE5 10BASE5 (also known as thick Ethernet or thicknet) was the first commercially available variant of Ethernet. The technology was standardized in 1982 as IEEE 802.3. 10BASE5 uses a thick and stiff coaxial cable up to in length. Up to 100 stati ...
. Since the RMII standard neglected to stipulate that TX_EN should only be sampled on alternate clock cycles, it is not symmetric with CRS_DV and two RMII PHY devices cannot be connected back to back to form a repeater; this is possible, however, with the National DP83848 which supplies the decoded RX_DV as a supplemental signal in RMII mode.


Signal levels

TTL
logic level In digital circuits, a logic level is one of a finite number of states that a digital signal can inhabit. Logic levels are usually represented by the voltage difference between the signal and ground, although other standards exist. The range ...
s are used for or logic. Input high threshold is and low is . The specification states that inputs should be tolerant, however, some popular chips with RMII interfaces are not tolerant. Newer devices may support and logic. The RMII signals are treated as lumped signals rather than
transmission line In electrical engineering, a transmission line is a specialized cable or other structure designed to conduct electromagnetic waves in a contained manner. The term applies when the conductors are long enough that the wave nature of the transmi ...
s. However, the IEEE version of the related MII standard specifies trace impedance.AN-1469 datasheet
/ref> National recommends running traces with series termination resistors for either MII or RMII mode to reduce reflections. National also suggests that traces be kept under long and matched within on length to minimize skew.


Gigabit media-independent interface

The gigabit media-independent interface (GMII) is an interface between the
medium access control In IEEE 802 LAN/MAN standards, the medium access control (MAC, also called media access control) sublayer is the layer that controls the hardware responsible for interaction with the wired, optical or wireless transmission medium. The MAC sublay ...
(MAC) device and the physical layer (
PHY PHY is an abbreviation for the physical layer of the OSI model and refers to the circuitry required to implement physical layer functions. PHY or Phy may also refer to: * Phy, the drug methadone * Phetchabun Airport (IATA code), Thailand See ...
). The interface operates at speeds up to 1000 Mbit/s, implemented using a data interface clocked at 125 MHz with separate eight-bit data paths for receive and transmit, and is backwards compatible with the MII specification and can operate on fall-back speeds of 10 or 100 Mbit/s. The GMII interface was first defined for 1000BASE-X in IEEE 802.3z-1998 as clause 35, and subsequently incorporated into IEEE 802.3-2000 onwards.


Transmitter signals

There are two transmitter clocks. The clock used depends on whether the PHY is operating at gigabit or 10/100 Mbit/s speeds. For gigabit operation, the GTXCLK is supplied to the PHY and the TXD, TXEN, TXER signals are synchronized to this. For 10 or 100 Mbit/s operation, the TXCLK is supplied by the PHY and is used for synchronizing those signals. This operates at either 25 MHz for 100 Mbit/s or 2.5 MHz for 10 Mbit/s connections. In contrast, the receiver uses a single clock signal recovered from the incoming data.


Receiver signals


Management signals

The management interface controls the behavior of the PHY. It has the same set of registers as the MII, except that register #15 is the Extended Status register.


Reduced gigabit media-independent interface

The reduced gigabit media-independent interface (RGMII) uses half the number of data pins as are used in the GMII interface. This reduction is achieved by running half as many data lines at double speed, time multiplexing signals and by eliminating non-essential carrier-sense and collision-indication signals. Thus RGMII consists only of 14 pins, as opposed to GMII's 24 to 27. Data is clocked on rising and falling edges for 1000 Mbit/s, and on rising edges only for 10/100 Mbit/s. The RX_CTL signal carries RXDV (data valid) on the rising edge, and (RXDV xor RXER) on the falling edge. The TX_CTL signal likewise carries TXEN on rising edge and (TXEN xor TXER) on the falling edge. This is the case for both 1000 Mbit/s and 10/100 Mbit/s. The transmit clock signal is always provided by the MAC on the TXC line. The receive clock signal is always provided by the PHY on the RXC line. Source-synchronous clocking is used: the clock signal that is output (by either the PHY or the MAC) is synchronous with the data signals. This requires the PCB to be designed to add a 1.5–2 ns delay to the clock signal to meet the setup and hold times on the sink. RGMII v2.0 specifies an optional internal delay, obviating the need for the PCB designer to add delay; this is known as RGMII-ID. RGMII version 1.3 uses 2.5V CMOS, whereas RGMII version 2 uses 1.5V HSTL.


Serial gigabit media-independent interface

The serial gigabit media-independent interface (SGMII) is a variant of MII used for
Gigabit Ethernet In computer networking, Gigabit Ethernet (GbE or 1 GigE) is the term applied to transmitting Ethernet frames at a rate of a gigabit per second. The most popular variant, 1000BASE-T, is defined by the IEEE 802.3ab standard. It came into use ...
but can also carry 10/100 Mbit/s Ethernet. It uses differential pairs at 625 MHz clock frequency DDR for TX and RX data and TX and RX clocks. It differs from GMII by its low-power and low pin-count
8b/10b In telecommunications, 8b/10b is a line code that maps 8-bit words to 10-bit symbols to achieve DC balance and bounded disparity, and at the same time provide enough state changes to allow reasonable clock recovery. This means that the diffe ...
-coded
SerDes {{Use American English, date = March 2019 A Serializer/Deserializer (SerDes) is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and paral ...
. Transmit and receive path each use one differential pair for data and another differential pair for clock. The TX/RX clocks must be generated on device output but are optional on device input (
clock recovery In serial communication of digital data, clock recovery is the process of extracting timing information from a serial data stream itself, allowing the timing of the data in the stream to be accurately determined without separate clock information. ...
may be used alternatively). 10/100 Mbit/s Ethernet is carried by duplicating data words 100/10 times each, so the clock is always at 625 MHz.


High serial gigabit media independent interface

The high serial gigabit media-independent interface (HSGMII) is functionally similar to the SGMII but supports link speeds of up to 2.5 Gbit/s.


Quad serial gigabit media-independent interface

The quad serial gigabit media-independent interface (QSGMII) is a method of combining four SGMII lines into a 5 Gbit/s interface. QSGMII, like SGMII, uses
low-voltage differential signaling Low-voltage differential signaling (LVDS), also known as TIA/EIA-644, is a technical standard that specifies electrical characteristics of a differential, serial signaling standard. LVDS operates at low power and can run at very high speeds ...
(LVDS) for the TX and RX data, and a single LVDS clock signal. QSGMII uses significantly fewer signal lines than four separate SGMII connections.


10 gigabit media-independent interface

10 gigabit media-independent interface (XGMII) is a standard defined in IEEE 802.3 designed for connecting full duplex
10 Gigabit Ethernet 10 Gigabit Ethernet (10GE, 10GbE, or 10 GigE) is a group of computer networking technologies for transmitting Ethernet frames at a rate of 10  gigabits per second. It was first defined by the IEEE 802.3ae-2002 standard. Unlike previous ...
(10GbE) ports to each other and to other electronic devices on a printed circuit board (PCB). It is now typically used for on-chip connections. PCB connections are now mostly accomplished with
XAUI 10 Gigabit Attachment Unit Interface (XAUI ) is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between the MAC and PHY layer of 10 Gigabit Ethernet (10GbE) defined in Clause 47 of the IEEE 802.3 standard. The name i ...
. XGMII features two 32-bit datapaths (Rx & Tx) and two four-bit control flows (Rxc and Txc), operating at 156.25 MHz
DDR DDR or ddr may refer to: *ddr, ISO 639-3 code for the Dhudhuroa language *DDr., title for a double doctorate in Germany *DDR, station code for Dadar railway station, Mumbai, India *' (German Democratic Republic), official name of the former East ...
(312.5 
MT/s In computer technology, transfers per second and its more common secondary terms gigatransfers per second (abbreviated as GT/s) and megatransfers per second (MT/s) are informal language that refer to the number of operations transferring data that ...
).


See also

*
Attachment Unit Interface The Attachment Unit Interface (AUI) is a physical and logical interface defined in the original IEEE 802.3 standard for 10BASE5 Ethernet and the previous DIX standard. The physical interface consists of a 15-pin D-subminiature connection that ...
(AUI) *
G.hn G.hn is a specification for home networking with data rates up to 2 Gbit/s and operation over four types of legacy wires: telephone wiring, coaxial cables, power lines and plastic optical fiber. A single G.hn semiconductor device is able to n ...
, an
ITU-T The ITU Telecommunication Standardization Sector (ITU-T) is one of the three sectors (divisions or units) of the International Telecommunication Union (ITU). It is responsible for coordinating standards for telecommunications and Information Comm ...
recommendation that uses the term MII to refer to the interface between the
data link layer The data link layer, or layer 2, is the second layer of the seven-layer OSI model of computer networking. This layer is the protocol layer that transfers data between nodes on a network segment across the physical layer. The data link layer ...
and the physical layer. *
Gigabit interface converter A gigabit interface converter (GBIC) is a standard for transceivers, first defined in 1995 and commonly used with Gigabit Ethernet and Fibre Channel for some time. By offering a standard, hot swappable electrical interface, a single gigabit po ...
(GBIC) * List of interface bit rates *
Medium-dependent interface A medium dependent interface (MDI) describes the interface (both physical and electrical/optical) in a computer network from a physical layer implementation to the physical medium used to carry the transmission. Ethernet over twisted pair also d ...
(MDI) *
Small form-factor pluggable transceiver Small Form-factor Pluggable connected to a pair of fiber-optic cables Small Form-factor Pluggable (SFP) is a compact, hot-pluggable network interface module format used for both telecommunication and data communications applications. An SF ...
(SFP) * *
XFP transceiver The XFP (10 gigabit small form-factor pluggable) is a standard for transceivers for high-speed computer network and telecommunication links that use optical fiber. It was defined by an industry group in 2002, along with its interface to other e ...


References


External links


Texas Instruments AN-1405 DP83848 RMII

Texas Instruments DP83848C PHY Data Sheet

hp.com RGMIIv2_0_final_hp.pdf RGMII 2002-04-01 Version 2.0
* *


GMII Timing and Electrical Specification
{{Ethernet Ethernet Computer buses Serial buses