The Design Automation Standards Committee (DASC) is a subgroup of interested individuals members of the

Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers (IEEE) is a 501(c)(3) professional association for electronic engineering and electrical engineering (and associated disciplines) with its corporate office in New York City and its operat ...

(IEEE)

Computer Society The Institute of Electrical and Electronics Engineers (IEEE) is a 501(c)(3) professional association for electronic engineering and electrical engineering (and associated disciplines) with its corporate office in New York City and its operati ...

and Standards Association. It oversees IEEE Standards that are related to computer-aided design (known as design automation). It is part of the

IEEE Computer Society The Institute of Electrical and Electronics Engineers (IEEE) is a 501(c)(3) professional association for electronic engineering and electrical engineering (and associated disciplines) with its corporate office in New York City and its operati ...

. This group sponsors and develops standards under the policies of the

IEEE The Institute of Electrical and Electronics Engineers (IEEE) is a 501(c)(3) professional association for electronic engineering and electrical engineering (and associated disciplines) with its corporate office in New York City and its operati ...

. The group started in the summer of 1984 at the

Design Automation Conference The Design Automation Conference, or DAC, is an annual event, a combination of a technical conference and a trade show, both specializing in electronic design automation (EDA). DAC is the oldest and largest conference in EDA, started in 1964. ...

. Initially, the group supported

VHDL The VHSIC Hardware Description Language (VHDL) is a hardware description language (HDL) that can model the behavior and structure of digital systems at multiple levels of abstraction, ranging from the system level down to that of logic gat ...

as a standard, but extended its coverage to

Verilog Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is a ...

, and then additional areas in the design automation space. After going through a period of very few meetings in 2004–06 which ended with some contention about Power standards (see

Common Power Format The Si2 Common Power Format, or CPF is a file format for specifying power-saving techniques early in the design process. In the design of integrated circuits, saving power is a primary goal, and designers are forced to use sophisticated techniques ...

and

Unified Power Format Unified Power Format (UPF) is the popular name of the Institute of Electrical and Electronics Engineers (IEEE) standard for specifying power intent in power optimization of electronic design automation. The IEEE 1801-2009 release of the standard ...

), the group developed new and explici
policies and procedures
With these procedures approved in 2007, the group began meeting monthly via teleconference. Active meetings include EDA companies, System integration companies, Electronic Intellectual Property (IP developers, and Semiconductor companies, and individuals interested in these topics. Beginning in 2007, the group began to award the Ron Waxman Design Automation Standards Committee Meritorious Service Award. This award was named after the early and consistently contributing organizer of the DASC, Ron Waxman. The first recipient of the award in 2007 was Gabe Moretti.

Work of the committee

The biggest center of interest in the DASC has been around language based design and verification standards stemming from the key

hardware description language In computer engineering, a hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, and most commonly, digital logic circuits. A hardware description language e ...

standards

and

. From these have flowed standards for timing, synthesis, math routines, test, power, encryption, and meta-data for the topics above. The emphasis of the group has also grown to embrace standards being developed in analog-mixed signal and other extensions driven by these needs. The active Working Groups are: *VHDL Working Groups **P1076 Standard

Language Reference Manual
VASG
**P1076.1 Standard VHDL Analog and Mixed-Signal Extensions
VHDL-AMS
**P1076.1.1 Standard VHDL Analog and Mixed-Signal Extensions - Packages for Multiple Energy Domain Support

- this group is now part of 1076.1 *SystemVerilog Working Groups **P1800

SystemVerilog SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems. SystemVerilog is based on Verilog and some extensions, and since 20 ...

: Unified Hardware Design, Specification and Verification Language
SV-IEEE1800
osponsored with IEEE-SA CAG*P1647 Standard for the Functional Verification Language 'e'
eWG
*P1699 Rosetta System Level Design Language Standard
WG
*P1734 Standard for Electronic Design Intellectual Property (IP) Quality
WG
*P1801 Standard for the Design & Verification of Low Power ICs The inactive Working Groups are: *P1076.2 IEEE Standard VHDL Mathematical Packages
math
*P1076.3 Standard VHDL Synthesis Packages
vhdlsynth
*P1164 Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164)
vhdl-std-logic
*P1076.4 Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification
VITAL
- This group is now part of 1076.
VHDL-200x
the next revision *Issues Screening and Analysis Committee
ISAC
*VHDL Programming Language Interface Task Force
VHPI
*P1364 Standard for

Hardware Description Language
IEEEVerilog
- this group is now part of P1800 *P1364.1 Standard for Verilog Register Transfer Level Synthesis
VLOG-Synth
*P1481 Standard for Integrated Circuit (IC) Open Library Architecture (OLA)
IEEE1481R
*P1497 Standard for

Standard Delay Format Standard Delay Format (SDF) is an IEEE standard for the representation and interpretation of timing data for use at any stage of an electronic design process. It finds wide applicability in design flows, and forms an efficient bridge between dynami ...

(SDF) for the Electronic Design Process
sdf
*P1499 Standard Interface for Hardware Description Models of Electronic Components
OMF
*P1577 Object Oriented VHDL
oovhdl
*P1603 Standard for an Advanced Library Format (ALF) Describing Integrated Circuit (IC) Technology, Cells, and Blocks
ALF
*P1604 Library IEEE
libieee
*P1076.6 Standard for VHDL Register Transfer Level (RTL) Synthesis
SIWG
*P1666 Standard System C Language Reference Manual
systemc
osponsored with IEEE-SA CAG*P1685 SPIRIT XML Standard for IP Description
IEEE-1685
*P1735 Recommended Practice for Encryption and se RightsManagement of Electronic Design Intellectual Property (IP)
WG
*P1778

ESTEREL Esterel is a synchronous programming language for the development of complex reactive systems. The imperative programming style of Esterel allows the simple expression of parallelism and preemption. As a consequence, it is well suited for cont ...

v7 Language Standardization
WG
*P1850 Standard for PSL:

Property Specification Language Property Specification Language (PSL) is a temporal logic extending linear temporal logic with a range of operators for both ease of expression and enhancement of expressive power. PSL makes an extensive use of regular expressions and syntactic suga ...

IEEE-1850
A project is designated by its IEEE-assigned number prefixed with the letter "P".

References

* *

External links

Design Automation Standards Committee
(DASC)
EDA Industry Working Groups
{{IEEE standards IEEE standards IEEE DASC standards Organizations established in 1984

Work of the committee

See also

References

External links