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Delay calculation is the term used in
integrated circuit design Integrated circuit design, or IC design, is a sub-field of electronics engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs. ICs consist of miniaturized electronic component ...
for the calculation of the
gate delay Propagation delay is the time duration taken for a signal to reach its destination. It can relate to networking, electronics or physics. ''Hold time'' is the minimum interval required for the logic level to remain on the input after triggering ed ...
of a single
logic gate A logic gate is an idealized or physical device implementing a Boolean function, a logical operation performed on one or more binary inputs that produces a single binary output. Depending on the context, the term may refer to an ideal logic gate, ...
and the wires attached to it. By contrast,
static timing analysis Static timing analysis (STA) is a simulation method of computing the expected timing of a Synchronous circuit, synchronous digital circuit without requiring a simulation of the full circuit. High-performance integrated circuits have tradition ...
computes the delays of entire paths, using delay calculation to determine the delay of each gate and wire. There are many methods used for delay calculation for the gate itself. The choice depends primarily on the speed and accuracy required: :*Circuit simulators such as
SPICE A spice is a seed, fruit, root, bark, or other plant substance primarily used for flavoring or coloring food. Spices are distinguished from herbs, which are the leaves, flowers, or stems of plants used for flavoring or as a garnish. Spices a ...
may be used. This is the most accurate, but slowest, method. :*Two dimensional tables are commonly used in applications such as
logic synthesis In computer engineering, logic synthesis is a process by which an abstract specification of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gates, typically by a compu ...
, placement and
routing Routing is the process of selecting a path for traffic in a network or between or across multiple networks. Broadly, routing is performed in many types of networks, including circuit-switched networks, such as the public switched telephone netw ...
. These tables take an output load and input slope and generate a circuit delay and output slope. The values of the tables are usually computed using circuit simulators in a procedure referred to as ''characterization'' or ''
standard cell In semiconductor design, standard cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. Standard cell methodology is an example of design abstraction, whereby a low-level v ...
characterization''. A common file format for storing the lookup tables is the ''Liberty'' format. :*A very simple model called the ''K-factor'' model is sometimes used. This approximates the delay as a constant plus ''k'' times the load capacitance. :*A more complex model called Delay Calculation Language, or DCL, calls a user-defined program whenever a delay value is required. This allows arbitrarily complex models to be represented, but raises significant software engineering issues. :*
Logical effort The method of logical effort, a term coined by Ivan Sutherland and Bob Sproull in 1991, is a straightforward technique used to estimate delay in a CMOS circuit. Used properly, it can aid in selection of gates for a given function (including the nu ...
provides a simple delay calculation that accounts for gate sizing and is analytically tractable. Similarly, there are many ways to calculate the delay of a wire. The delay of a wire will normally be different for each destination. In order to increase accuracy (and decrease speed), the most common methods are: :*''Lumped C''. The entire wire capacitance is applied to the gate output, and the delay through the wire itself is ignored. :*
Elmore delay Elmore delay is a simple approximation to the delay through an RC network in an electronic system. It is often used in applications such as logic synthesis, delay calculation, static timing analysis, placement and routing, since it is simple to ...
is a simple approximation, often used where speed of calculation is important but the delay through the wire itself cannot be ignored. It uses the R and C values of the wire segments in a simple calculation. The delay of each wire segment is the R of that segment times the downstream C. Then all delays are summed from the root. (This assumes the network is tree-structured, true of most nets in chips. In this case, the Elmore delay can be calculated in time O(N) with two tree traversals. If the network is not tree-structured the Elmore delay can still be computed, but involves matrix calculations.) :*''Moment matching'' is a more sophisticated analytical method. It can be thought of as either matching multiple moments in the time domain or finding a good rational approximation (a Padé approximation) in the frequency domain. (These are very closely related - see
Laplace transform In mathematics, the Laplace transform, named after its discoverer Pierre-Simon Laplace (), is an integral transform In mathematics, an integral transform maps a function from its original function space into another function space via integra ...
.) It can also be considered a generalization of Elmore delay, which matches the first moment in the time domain (or computes a one-pole approximation in the frequency domain - they are equivalent). The first use of this technique, AWE, used explicit moment matching. Newer methods such as PRIMA and PVL use implicit moment matching, based on
Krylov subspace In linear algebra, the order-''r'' Krylov subspace generated by an ''n''-by-''n'' matrix ''A'' and a vector ''b'' of dimension ''n'' is the linear subspace spanned by the images of ''b'' under the first ''r'' powers of ''A'' (starting from A^0=I), ...
s. These methods are slower than Elmore but more accurate. Compared to circuit simulation they are faster but less accurate. :*Circuit simulators such as
SPICE A spice is a seed, fruit, root, bark, or other plant substance primarily used for flavoring or coloring food. Spices are distinguished from herbs, which are the leaves, flowers, or stems of plants used for flavoring or as a garnish. Spices a ...
may be used. This is usually the most accurate, but slowest, method. :*DCL, as defined above, can be used for interconnecting as well as gate delay. Often, it makes sense to combine the calculation of a gate and all the wires connected to its output. This combination is often called the ''stage delay''. The delay of a wire or gate may also depend on the behaviour of the nearby components. This is one of the main effects that is analyzed during
signal integrity Signal integrity or SI is a set of measures of the quality of an electrical signal. In digital electronics, a stream of binary values is represented by a voltage (or current) waveform. However, digital signals are fundamentally analog in nature, ...
checks.


Delay calculation in digital design

In the context of semi-custom digital design, pre-characterized digital information is often abstracted in the form of the above-mentioned 2-D look-up table (LUT). The idea behind the semi-custom design method is to use blocks of pre-built and tested components to build something larger, say, a chip. In this context, the blocks are
logic gate A logic gate is an idealized or physical device implementing a Boolean function, a logical operation performed on one or more binary inputs that produces a single binary output. Depending on the context, the term may refer to an ideal logic gate, ...
s such as NAND, OR, AND, etc. Although, in reality, these gates will be composed of transistors, a semi-custom engineer will only be aware of the delay information from the input pin to the output pin, called a timing arc. The 2D table represents the variability of the gate's delay concerning the two independent variables, usually the rate of change of the signal at the input and the load at the output pin. These two variables are called slew and load in design parlance. A
static timing analysis Static timing analysis (STA) is a simulation method of computing the expected timing of a Synchronous circuit, synchronous digital circuit without requiring a simulation of the full circuit. High-performance integrated circuits have tradition ...
engine will first calculate the delay of the individual cells and string them together to do further analysis.


Statistical delay calculation

As chip dimensions get smaller, the delays of both gates and wires may need to be treated as statistical estimates instead of deterministic quantities. For gates, this requires extensions to the library formats. For wires, this requires methods that can calculate the means and distributions of wire delays. In both cases, it is critical to capture the dependence on the underlying variables, such as threshold voltage and metal thickness, since these result in correlations among the delays of nearby components. See Ying Liu; Pileggi, L.T.; Strojwas, A.J., (1999) , proceedings of the 36th Design Automation Conference, 21–25 June 1999, pp. 201 - 206 for an early example.


See also

*
Logical effort The method of logical effort, a term coined by Ivan Sutherland and Bob Sproull in 1991, is a straightforward technique used to estimate delay in a CMOS circuit. Used properly, it can aid in selection of gates for a given function (including the nu ...
*
Propagation delay Propagation delay is the time duration taken for a signal to reach its destination. It can relate to networking, electronics or physics. ''Hold time'' is the minimum interval required for the logic level to remain on the input after triggering e ...
*
Electronic design automation Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD), is a category of software tools for designing Electronics, electronic systems such as integrated circuits and printed circuit boards. The tools wo ...
*
Integrated circuit design Integrated circuit design, or IC design, is a sub-field of electronics engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs. ICs consist of miniaturized electronic component ...
*
Static timing analysis Static timing analysis (STA) is a simulation method of computing the expected timing of a Synchronous circuit, synchronous digital circuit without requiring a simulation of the full circuit. High-performance integrated circuits have tradition ...
* Statistical static timing analysis * Standard Parasitic Exchange Format


References

{{DEFAULTSORT:Delay Calculation Timing in electronic circuits