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On the
x86 architecture x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel, based on the 8086 microprocessor and its 8-bit-external-bus variant, the 8088. T ...
, a debug register is a register used by a processor for program
debugging In engineering, debugging is the process of finding the Root cause analysis, root cause, workarounds, and possible fixes for bug (engineering), bugs. For software, debugging tactics can involve interactive debugging, control flow analysis, Logf ...
. There are six debug registers, named DR0...DR7, with DR4 and DR5 as obsolete synonyms for DR6 and DR7. The debug registers allow programmers to selectively enable various debug conditions associated with a set of four debug addresses. Two of these registers are used to control debug features. These registers are accessed by variants of the MOV instruction. A debug register may be either the source operand or destination operand. The debug registers are privileged resources; the MOV instructions that access them can only be executed at privilege level zero. An attempt to read or write the debug registers when executing at any other privilege level causes a general protection fault.


DR0 to DR3

Each of these registers contains the linear address associated with one of four breakpoint conditions. Each
breakpoint In software development, a breakpoint is an intentional stopping or pausing place in a computer program, program, put in place for debugging purposes. It is also sometimes simply referred to as a pause. More generally, a breakpoint is a means o ...
condition is further defined by bits in DR7. The debug address registers are effective whether or not
paging In computer operating systems, memory paging is a memory management scheme that allows the physical Computer memory, memory used by a program to be non-contiguous. This also helps avoid the problem of memory fragmentation and requiring compact ...
is enabled. The addresses in these registers are linear addresses. If paging is enabled, the linear addresses are translated into
physical address In computing, a physical address (also real address, or binary address), is a memory address that is represented in the form of a binary number on the address bus circuitry in order to enable the data bus to access a ''particular'' storage cell o ...
es by the processor's paging mechanism. If paging is not enabled, these linear addresses are the same as physical addresses. Note that when paging is enabled, different tasks may have different linear-to-physical address mappings. When this is the case, an address in a debug address register may be relevant to one task but not to another. For this reason the x86 has both global and local enable bits in DR7. These bits indicate whether a given debug address has a global (all tasks) or local (current task only) relevance.


DR6 - Debug status

The debug status register permits the debugger to determine which debug conditions have occurred. When the processor detects an enabled debug exception, it will set the corresponding bits of this register before entering the debug exception handler.


DR7 - Debug control

The debug control register is used to selectively enable the four address breakpoint conditions, and to specify the type and size of each of the four breakpoints. There are two levels of enabling: the local (0,2,4,6) and global (1,3,5,7) levels. The local enable bits are automatically reset by the processor at every task switch to avoid unwanted breakpoint conditions in the new task. The global enable bits are not reset by a task switch; therefore, they can be used for conditions that are global to all tasks.


DR4 and DR5

Not real registers. On processors that support the CR4.DE bit (Intel
Pentium Pentium is a series of x86 architecture-compatible microprocessors produced by Intel from 1993 to 2023. The Pentium (original), original Pentium was Intel's fifth generation processor, succeeding the i486; Pentium was Intel's flagship proce ...
and later), their behaviour is controlled by CR4.DE: * CR4.DE=0 : DR4 and DR5 alias to DR6 and DR7, respectively. * CR4.DE=1 : accessing DR4/5 results in #UD (invalid opcode) exception. On processors without CR4.DE, the behaviour is officially undefined - usually, DR4/5 are aliased to DR6/7, but exceptions exist and have been used for CPU detection.Geoff Chappell
CPU Identification Before CPUID
4 Mar 2023. Accessed on 6 Sep 2024

on 3 Jun 2024.


See also

* Control register * Test register


References

{{reflist * Intel 80386 Programmer's Reference


External links

* http://www.codeproject.com/KB/debug/hardwarebreakpoint.aspx Using the debug registers in Windows. X86 instructions Operating system technology Digital registers Debugging