In
integrated circuits (ICs), interconnects are structures that connect two or more circuit elements (such as transistors) together electrically. The design and layout of interconnects on an IC is vital to its proper function, performance, power efficiency, reliability, and
fabrication yield. The material interconnects are made from depends on many factors. Chemical and mechanical compatibility with the
semiconductor
A semiconductor is a material which has an electrical conductivity value falling between that of a conductor, such as copper, and an insulator, such as glass. Its resistivity falls as its temperature rises; metals behave in the opposite way. ...
substrate and the
dielectric
In electromagnetism, a dielectric (or dielectric medium) is an electrical insulator that can be polarised by an applied electric field. When a dielectric material is placed in an electric field, electric charges do not flow through the mate ...
between the levels of interconnect is necessary, otherwise barrier layers are needed. Suitability for fabrication is also required; some chemistries and processes prevent the integration of materials and unit processes into a larger technology (recipe) for IC fabrication. In fabrication, interconnects are formed during the
back-end-of-line after the fabrication of the transistors on the substrate.
Interconnects are classified as ''local'' or ''global'' interconnects depending on the signal propagation distance it is able to support. The width and thickness of the interconnect, as well as the material from which it is made, are some of the significant factors that determine the distance a signal may propagate. Local interconnects connect circuit elements that are very close together, such as transistors separated by ten or so other contiguously laid out transistors. Global interconnects can transmit further, such as over large-area sub-circuits. Consequently, local interconnects may be formed from materials with relatively high
electrical resistivity
Electrical resistivity (also called specific electrical resistance or volume resistivity) is a fundamental property of a material that measures how strongly it resists electric current. A low resistivity indicates a material that readily allows ...
such as
polycrystalline silicon (sometimes
silicide
A silicide is a type of chemical compound that combines silicon and a (usually) more electropositive element.
Silicon is more electropositive than carbon. Silicides are structurally closer to borides than to carbides.
Similar to borides and carb ...
d to extend its range) or
tungsten
Tungsten, or wolfram, is a chemical element with the symbol W and atomic number 74. Tungsten is a rare metal found naturally on Earth almost exclusively as compounds with other elements. It was identified as a new element in 1781 and first isol ...
. To extend the distance an interconnect may reach, various circuits such as buffers or restorers may be inserted at various points along a long interconnect.
Interconnect properties
The geometric properties of an interconnect are width, thickness, spacing (the distance between an interconnect and another on the same level), pitch (the sum of the width and spacing), and aspect ratio, or AR, (the thickness divided by width). The width, spacing, AR, and ultimately, pitch, are constrained in their minimum and maximum values by
design rules that ensure the interconnect (and thus the IC) can be fabricated by the selected technology with a reasonable yield. Width is constrained to ensure minimum width interconnects do not suffer breaks, and maximum width interconnects can be planarized by
chemical mechanical polishing (CMP). Spacing is constrained to ensure adjacent interconnects can be fabricated without any conductive material bridging. Thickness is determined solely by the technology, and the aspect ratio, by the chosen width and set thickness. In technologies that support multiple levels of interconnects, each group of contiguous levels, or each level, has its own set of design rules.
Before the introduction of CMP for planarizing IC layers, interconnects had design rules that specified larger minimum widths and spaces than the lower level to ensure that the underlying layer's rough topology did not cause breaks in the interconnect formed on top. The introduction of CMP has made finer geometries possible.
The AR is an important factor. In technologies that form interconnect structures with conventional processes, the AR is limited to ensure that the etch creating the interconnect, and the dielectric deposition that fills the voids in between interconnects with dielectric, can be done successfully. In those that form interconnect structures with damascene processes, the AR must permit successful etch of the trenches, deposition of the barrier metal (if needed) and interconnect material.
Interconnect layout are further restrained by design rules that apply to collections of interconnects. For a given area, technologies that rely on CMP have ''density rules'' to ensure the whole IC has an acceptable variation in interconnect density. This is because the rate at which CMP removes material depends on the material's properties, and great variations in interconnect density can result in large areas of dielectric which can dish, resulting in poor planarity. To maintain acceptable density, ''dummy interconnects'' (or ''dummy wires'') are inserted into regions with spare interconnect density.
Historically, interconnects were routed in straight lines, and could change direction by using sections aligned 45° away from the direction of travel. As IC structure geometries became smaller, to obtain acceptable yields, restrictions were imposed on interconnect direction. Initially, only global interconnects were subject to restrictions; were made to run in straight lines aligned eastwest or northsouth. To allow easy routing, alternate levels of interconnect ran in the same alignment, so that changes in direction were achieved by connecting to a lower or upper level of interconnect though a via. Local interconnects, especially the lowest level (usually polysilicon) could assume a more arbitrary combination of routing options to attain the a higher packing density.
Materials
In
silicon
Silicon is a chemical element with the symbol Si and atomic number 14. It is a hard, brittle crystalline solid with a blue-grey metallic luster, and is a tetravalent metalloid and semiconductor. It is a member of group 14 in the periodic ta ...
ICs, the most commonly used semiconductor in ICs, the first interconnects were made of aluminum. Aluminum was an ideal material for interconnects due to its ease of deposition and good adherence to silicon and silicon dioxide. Al interconnects are deposited by
physical vapor deposition
Physical vapor deposition (PVD), sometimes called physical vapor transport (PVT), describes a variety of vacuum deposition methods which can be used to produce thin films and coatings on substrates including metals, ceramics, glass, and polym ...
or
chemical vapor deposition methods. They were originally patterned by
wet etching, and later by various
dry etching
Dry etching refers to the removal of material, typically a masked pattern of semiconductor material, by exposing the material to a bombardment of ions (usually a plasma of reactive gases such as fluorocarbons, oxygen, chlorine, boron trichloride; ...
techniques.
Initially, pure aluminum was used but by the 1970s, substrate compatibility, junction spiking and reliability concerns (mostly concerning
electromigration) forced the use of aluminum-based
alloy
An alloy is a mixture of chemical elements of which at least one is a metal. Unlike chemical compounds with metallic bases, an alloy will retain all the properties of a metal in the resulting material, such as electrical conductivity, ductilit ...
s containing silicon,
copper
Copper is a chemical element with the symbol Cu (from la, cuprum) and atomic number 29. It is a soft, malleable, and ductile metal with very high thermal and electrical conductivity. A freshly exposed surface of pure copper has a pinkis ...
, or both. By the late 1990s, the high resistivity of aluminum, coupled with the narrow widths of the interconnect structures forced by continuous
feature size downscaling, resulted in prohibitively high resistance in interconnect structures. This forced aluminum's replacement by
copper interconnects
In semiconductor technology, copper interconnects are interconnects made of copper. They are used in silicon integrated circuits (ICs) to reduce propagation delays and power consumption. Since copper is a better conductor than aluminium, ICs usi ...
.
In
gallium arsenide (GaAs) ICs, which have been mainly used in application domains (e.g.
monolithic microwave ICs) different to those of silicon, the predominant material used for interconnects is
gold
Gold is a chemical element with the symbol Au (from la, aurum) and atomic number 79. This makes it one of the higher atomic number elements that occur naturally. It is a bright, slightly orange-yellow, dense, soft, malleable, and ductile me ...
.
Performance enhancements
To reduce the delay penalty caused by
parasitic capacitance, the dielectric material used to insulate adjacent interconnects, and interconnects on different levels (the inter-level dielectric
LD, should have a
dielectric constant that is as close to 1 as possible. A class of such materials,
Low-κ dielectrics, were introduced during the late 1990s and early 2000s for this purpose. As of January 2019, the most advanced materials reduce the dielectric constant to very low levels through highly porous structures, or through the creation of substantial air or
vacuum
A vacuum is a space devoid of matter. The word is derived from the Latin adjective ''vacuus'' for "vacant" or " void". An approximation to such vacuum is a region with a gaseous pressure much less than atmospheric pressure. Physicists often di ...
pockets (air gap dielectric). These materials often have low mechanical strength and are restricted to the lowest level or levels of interconnect as a result. The high density of interconnects at the lower levels, along with the minimal spacing, helps support the upper layers.
Intel
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the developers of the x86 seri ...
introduced air-gap dielectric in its
14nm technology in 2014.
Multi-level interconnects
IC with complex circuits require multiple levels of interconnect to form circuits that have minimal area. As of 2018, the most complex ICs may have over 15 layers of interconnect. Each level of interconnect is separated from each other by a layer of dielectric. To make vertical connections between interconnects on different levels,
vias are used. The top-most layers of a chip have the thickest and widest and most widely separated metal layers, which make the wires on those layers have the least resistance and smallest
RC time constant
The RC time constant, also called tau, the time constant (in seconds) of an RC circuit, is equal to the product of the circuit resistance (in ohms) and the circuit capacitance (in farads), i.e.
: \tau = RC econds
It is the time required to c ...
, so they are used for power and
clock distribution network
In electronics and especially synchronous digital circuits, a clock signal (historically also known as ''logic beat'') oscillates between a high and a low state and is used like a metronome to coordinate actions of digital circuits.
A clock sig ...
s. The bottom-most metal layers of the chip, closest to the transistors, have thin, narrow, tightly-packed wires, used only for local interconnect. Adding layers can potentially improve performance, but adding layers also reduces yield and increases manufacturing costs. ICs with a single metal layer typically use the polysilicon layer to "jump across" when one signal needs to cross another signal.
The process used to form
DRAM capacitors creates a rough and hilly surface, which makes it difficult to add metal interconnect layers and still maintain good yield.
In 1998, state-of-the-art DRAM processes had four metal layers, while state-of-the-art logic processes had seven metal layers.
In 2002, five or six layers of metal interconnect was common.
In 2009, 1Gbit DRAM typically had three layers of metal interconnect; tungsten for the first layer and aluminum for the upper layers.
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See also
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Antenna effect
The antenna effect, more formally plasma induced gate oxide damage, is an effect that can potentially cause yield and reliability problems during the manufacture of MOS integrated circuits. Factories (''fabs'') normally supply antenna rules, wh ...
*
Bonding pad
Contact pads or bond pads are designated surface areas of a printed circuit board (PCB) or die of an integrated circuit.
Possibilities to contact to pads include soldering, wirebonding, flip chip
Flip chip, also known as controlled colla ...
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Carbon nanotubes in interconnects
In nanotechnology, carbon nanotube interconnects refer to the proposed use of carbon nanotubes in the Interconnects (integrated circuits), interconnects between the elements of an integrated circuit. Carbon nanotubes (CNTs) can be thought of as sin ...
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Interconnect bottleneck
The interconnect bottleneck comprises limits on integrated circuit (IC) performance due to connections between components instead of their internal speed.
In 2006 it was predicted to be a "looming crisis" by 2010.
Improved performance of computer ...
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Optical interconnect
In integrated circuits, optical interconnects refers to any system of transmitting signals from one part of an integrated circuit to another using light. Optical interconnects have been the topic of study due to the high latency and power consumpt ...
*
Parasitic extraction In electronic design automation, parasitic extraction is the calculation of the parasitic effects in both the designed devices and the required wiring interconnects of an electronic circuit: parasitic capacitances, parasitic resistances and parasi ...
References
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Integrated circuits
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