The ARM Cortex-X1 is a
central processing unit
A central processing unit (CPU), also called a central processor, main processor or just processor, is the electronic circuitry that executes instructions comprising a computer program. The CPU performs basic arithmetic, logic, controlling, an ...
implementing the
ARMv8.2-A
AArch64 or ARM64 is the 64-bit extension of the ARM architecture family.
It was first introduced with the Armv8-A architecture. Arm releases a new extension every year.
ARMv8.x and ARMv9.x extensions and features
Announced in October 2011, AR ...
64-bit
instruction set
In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an ' ...
designed by
ARM Holdings
Arm is a British semiconductor and software design company based in Cambridge, England.
Its primary business is in the design of ARM processors (CPUs). It also designs other chips, provides software development tools under the DS-5, RealView an ...
'
Austin
Austin is the capital city of the U.S. state of Texas, as well as the seat and largest city of Travis County, with portions extending into Hays and Williamson counties. Incorporated on December 27, 1839, it is the 11th-most-populous city ...
design centre as part of ARM's Cortex-X Custom (CXC) program.
Design
The Cortex-X1 design is based on the
ARM Cortex-A78
The ARM Cortex-A78 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Ltd.'s Austin centre, set to be distributed amongst high-end devices in 2020–2021.
Design
The ARM Cortex-A78 is the successor t ...
, but redesigned for purely performance instead of a balance of performance, power, and area (PPA).
The Cortex-X1 is a 5-wide decode
out-of-order superscalar
A superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a scalar processor, which can execute at most one single instruction per clock cycle, a sup ...
design with a 3K macro-OP (MOPs) cache. It can fetch 5 instructions and 8 MOPs per cycle, and rename and dispatch 8 MOPs, and 16 µOPs per cycle. The out-of-order window size has been increased to 224 entries. The backend has 15 execution ports with a pipeline depth of 13 stages and the execution latencies consists of 10 stages. It also features 4x128b SIMD units.
ARM claims the Cortex-X1 offers 30% faster integer and 100% faster machine learning performance than the
ARM Cortex-A77
The ARM Cortex-A77 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Austin design centre. ARM announced an increase of 23% and 35% in integer and floating point performance, respectively. M ...
.
The Cortex-X1 supports
ARM's DynamIQ technology, expected to be used as high-performance cores when used in combination with the
ARM Cortex-A78
The ARM Cortex-A78 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Ltd.'s Austin centre, set to be distributed amongst high-end devices in 2020–2021.
Design
The ARM Cortex-A78 is the successor t ...
mid and
ARM Cortex-A55
The ARM Cortex-A55 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Cambridge design centre. The Cortex-A55 is a 2-wide decode in-order superscalar pipeline.
Design
The Cortex-A55 serve ...
little cores.
Architecture changes in comparison with
ARM Cortex-A78
The ARM Cortex-A78 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Ltd.'s Austin centre, set to be distributed amongst high-end devices in 2020–2021.
Design
The ARM Cortex-A78 is the successor t ...
* Around 20% performance improvement (+30% from A77)
** 30% faster integer
** 100% faster machine learning performance
* Out-of-order window size has been increased to 224 entries (from 160 entries)
* Up to 4x128b SIMD units (from 2x128b)
* 15% more silicon area
* 5-way decode (from 4-way)
* 8 MOPs/cycle decoded cache bandwidth (from 6 MOPs/cycle)
* 64 KB L1D + 64 KB L1I (from 32/64 KB L1)
* Up to 1 MB/core L2 cache (from 512 KB/core max)
* Up to 8 MB L3 cache (from 4 MB max)
Licensing
The Cortex-X1 is available as
SIP core to partners of their Cortex-X Custom (CXC) program, and its design makes it suitable for integration with other SIP cores (e.g.
GPU
A graphics processing unit (GPU) is a specialized electronic circuit designed to manipulate and alter memory to accelerate the creation of images in a frame buffer intended for output to a display device. GPUs are used in embedded systems, mobil ...
,
display controller
A video display controller or VDC (also called a display engine or display interface) is an integrated circuit which is the main component in a video-signal generator, a device responsible for the production of a TV video signal in a computing ...
,
DSP
DSP may refer to:
Computing
* Digital signal processing, the mathematical manipulation of an information signal
* Digital signal processor, a microprocessor designed for digital signal processing
* Yamaha DSP-1, a proprietary digital signal ...
,
image processor
An image processor, also known as an image processing engine, image processing unit (IPU), or image signal processor (ISP), is a type of media processor or specialized digital signal processor (DSP) used for image processing, in digital cameras or ...
, etc.) into one
die
Die, as a verb, refers to death, the cessation of life.
Die may also refer to:
Games
* Die, singular of dice, small throwable objects used for producing random numbers
Manufacturing
* Die (integrated circuit), a rectangular piece of a semicondu ...
constituting a
system on a chip
A system on a chip or system-on-chip (SoC ; pl. ''SoCs'' ) is an integrated circuit that integrates most or all components of a computer or other electronic system. These components almost always include a central processing unit (CPU), memory ...
(SoC).
Usage
* Samsung
Exynos 2100
* Qualcomm
Snapdragon 888(+)
*
Google Tensor
Google Tensor is a series of ARM64-based system-on-chip (SoC) processors designed by Google for its Pixel devices. The first-generation chip debuted on the Pixel 6 smartphone series in 2021, and were succeeded by the second-generation chip on ...
See also
*
ARM Cortex-A78
The ARM Cortex-A78 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Ltd.'s Austin centre, set to be distributed amongst high-end devices in 2020–2021.
Design
The ARM Cortex-A78 is the successor t ...
, related high performance microarchitecture
*
Comparison of ARMv8-A cores
This is a comparison of processors based on the ARM family of instruction sets designed by ARM Holdings and 3rd parties, sorted by version of the ARM instruction set, release and name.
ARMv6
ARMv7-A
This is a table comparing central proc ...
, ARMv8 family
References
ARM processors
{{Comp-eng-stub