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Interrupt Coalescing
Interrupt coalescing, also known as interrupt moderation, is a technique in which events which would normally trigger a hardware interrupt are held back, either until a certain amount of work is pending, or a timeout timer triggers. Used correctly, this technique can reduce interrupt load by up to an order of magnitude, while only incurring relatively small latency penalties. Interrupt coalescing is typically combined with either a hardware FIFO or direct memory access, to allow for continued data throughput while interrupts are being held back. Interrupt coalescing is a common feature of modern network cards, but the technique dates back to early computer UARTs such as the 16550 UART chip used in the IBM PC's serial interface, at a time when even servicing the interrupt rates required by the low data rate serial data streams of the day was taxing for contemporary CPUs. Interrupt coalescing can also be implemented without support in hardware, by disabling interrupts in the inte ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Hardware Interrupt
In digital computers, an interrupt (sometimes referred to as a trap) is a request for the processor to ''interrupt'' currently executing code (when permitted), so that the event can be processed in a timely manner. If the request is accepted, the processor will suspend its current activities, save its state, and execute a function called an ''interrupt handler'' (or an ''interrupt service routine'', ISR) to deal with the event. This interruption is often temporary, allowing the software to resume normal activities after the interrupt handler finishes, although the interrupt could instead indicate a fatal error. Interrupts are commonly used by hardware devices to indicate electronic or physical state changes that require time-sensitive attention. Interrupts are also commonly used to implement computer multitasking, especially in real-time computing. Systems that use interrupts in these ways are said to be interrupt-driven. Types Interrupt signals may be issued in response to ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Timeout (computing)
In telecommunications and related engineering (including computer networking and programming), the term timeout or time-out has several meanings, including: * A network parameter related to an enforced event designed to occur at the conclusion of a predetermined elapsed time. * A specified period of time that will be allowed to elapse in a system before a specified event is to take place, unless another specified event occurs first; in either case, the period is terminated when either event takes place. Note: A timeout condition can be canceled by the receipt of an appropriate time-out cancellation signal. * An event that occurs at the end of a predetermined period of time that began at the occurrence of another specified event. The timeout can be prevented by an appropriate signal. Timeouts allow for more efficient usage of limited resources without requiring additional interaction from the agent interested in the goods that cause the consumption of these resources. The bas ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Direct Memory Access
Direct memory access (DMA) is a feature of computer systems and allows certain hardware subsystems to access main system memory independently of the central processing unit (CPU). Without DMA, when the CPU is using programmed input/output, it is typically fully occupied for the entire duration of the read or write operation, and is thus unavailable to perform other work. With DMA, the CPU first initiates the transfer, then it does other operations while the transfer is in progress, and it finally receives an interrupt from the DMA controller (DMAC) when the operation is done. This feature is useful at any time that the CPU cannot keep up with the rate of data transfer, or when the CPU needs to perform work while waiting for a relatively slow I/O data transfer. Many hardware systems use DMA, including disk drive controllers, graphics cards, network cards and sound cards. DMA is also used for intra-chip data transfer in multi-core processors. Computers that have DMA channels can trans ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
UART
A universal asynchronous receiver-transmitter (UART ) is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable. It sends data bits one by one, from the least significant to the most significant, framed by start and stop bits so that precise timing is handled by the communication channel. The electric signaling levels are handled by a driver circuit external to the UART. Two common signal levels are RS-232, a 12-volt system, and RS-485, a 5-volt system. Early teletypewriters used current loops. It was one of the earliest computer communication devices, used to attach teletypewriters for an operator console. It was also an early hardware system for the Internet. A UART is usually an individual (or part of an) integrated circuit (IC) used for serial communications over a computer or peripheral device serial port. One or more UART peripherals are commonly integrated in microcontroller chips. Specialised UA ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
16550 UART
The 16550 UART (universal asynchronous receiver/transmitter) is an integrated circuit designed for implementing the interface for serial communications. The corrected -A version was released in 1987 by National Semiconductor. It is frequently used to implement the serial port for IBM PC compatible personal computers, where it is often connected to an RS-232 interface for modems, serial mice, printers, and similar peripherals. It was the first serial chip used in the IBM PS/2 line, which were introduced in 1987. The part was originally made by National Semiconductor. Similarly numbered devices, with varying levels of compatibility with the original National Semiconductor part, are made by other manufacturers. A UART function that is register-compatible with the 16550 is usually a feature of multifunction I/O cards for IBM PC-compatible computers and may be integrated on the motherboard of other compatible computers. Replacement of the factory-installed 8250 UART was a common up ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
IBM PC
The IBM Personal Computer (model 5150, commonly known as the IBM PC) is the first microcomputer released in the IBM PC model line and the basis for the IBM PC compatible de facto standard. Released on August 12, 1981, it was created by a team of engineers and designers directed by Don Estridge in Boca Raton, Florida. The machine was based on open architecture and third-party peripherals. Over time, expansion cards and software technology increased to support it. The PC had a substantial influence on the personal computer market. The specifications of the IBM PC became one of the most popular computer design standards in the world. The only significant competition it faced from a non-compatible platform throughout the 1980s was from the Apple Macintosh product line. The majority of modern personal computers are distant descendants of the IBM PC. History Prior to the 1980s, IBM had largely been known as a provider of business computer systems. As the 1980s opened, their ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Polling (computer Science)
Polling, or polled operation, in computer science, refers to actively sampling the status of an external device by a client program as a synchronous activity. Polling is most often used in terms of input/output (), and is also referred to as polled or software-driven . A good example of hardware implementation is a watchdog timer. Description Polling is the process where the computer or controlling device waits for an external device to check for its readiness or state, often with low-level hardware. For example, when a printer is connected via a parallel port, the computer waits until the printer has received the next character. These processes can be as minute as only reading one bit. This is sometimes used synonymously with 'busy-wait' polling. In this situation, when an operation is required, the computer does nothing other than check the status of the device until it is ready, at which point the device is accessed. In other words, the computer waits until the device is ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
I/O Processor
In computing, channel I/O is a high-performance input/output (I/O) architecture that is implemented in various forms on a number of computer architectures, especially on mainframe computers. In the past, channels were generally implemented with custom devices, variously named channel, I/O processor, I/O controller, I/O synchronizer, or ''DMA controller''. Overview Many I/O tasks can be complex and require logic to be applied to the data to convert formats and other similar duties. In these situations, the simplest solution is to ask the CPU to handle the logic, but because I/O devices are relatively slow, a CPU could waste time (in computer perspective) waiting for the data from the device. This situation is called 'I/O bound'. Channel architecture avoids this problem by processing some or all of the I/O task without the aid of the CPU by offloading the work to dedicated logic. Channels are logically self-contained, with sufficient logic and working storage to handle I/O tasks. ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Timer Coalescing
Timer coalescing is a computer system energy-saving technique that reduces central processing unit (CPU) power consumption by reducing the precision of software timers used for synchronization of process wake-ups, minimizing the number of times the CPU is forced to perform the relatively power-costly operation of entering and exiting idle states. Implementations of timer coalescing *The Linux kernel gained support for deferrable timers in 2.6.22, and controllable "timer slack" for threads in 2.6.28 allowing timer coalescing. *Timer coalescing has been a feature of Microsoft Windows from Windows 7 onward. *Apple's XNU kernel based OS X gained support as of OS X Mavericks. * FreeBSD supports it since September 2010. See also * Advanced Configuration and Power Interface (ACPI) * Advanced Programmable Interrupt Controller (APIC) * High Precision Event Timer (HPET) * HLT (x86 instruction) * Interrupt coalescing * Programmable interval timer * Time Stamp Counter The Time ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
