A UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART /ˈjuːɑːrt/ ) is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable. The electric signaling levels and methods are handled by a driver circuit external to the UART. A UART is usually an individual (or part of an) integrated circuit (IC) used for serial communications over a computer or peripheral device serial port . UARTs are now commonly included in microcontrollers. A related device, the Universal Synchronous/Asynchronous Receiver/Transmitter (USART) also supports synchronous operation.
* 1 Transmitting and receiving serial data
* 1.1 Data framing * 1.2 Receiver * 1.3 Transmitter * 1.4 Application
* 2 History * 3 Structure
* 4.1 Overrun error * 4.2 Underrun error * 4.3 Framing error * 4.4 Parity error * 4.5 Break condition
* 5 UART models * 6 UART in modems * 7 See also * 8 References * 9 Further reading * 10 External links
TRANSMITTING AND RECEIVING SERIAL DATA
See also: Asynchronous serial communication
The universal asynchronous receiver/transmitter (UART) takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes. Each UART contains a shift register , which is the fundamental method of conversion between serial and parallel forms. Serial transmission of digital information (bits) through a single wire or other medium is less costly than parallel transmission through multiple wires.
The UART usually does not directly generate or receive the external signals used between different items of equipment. Separate interface devices are used to convert the logic level signals of the UART to and from the external signalling levels, which may be standardized voltage levels, current levels, or other signals.
Communication may be simplex (in one direction only, with no provision for the receiving device to send information back to the transmitting device), full duplex (both devices send and receive at the same time) or half duplex (devices take turns transmitting and receiving).
The idle, no data state is high-voltage, or powered. This is a
historic legacy from telegraphy, in which the line is held high to
show that the line and transmitter are not damaged. Each character is
framed as a logic low start bit, data bits, possibly a parity bit, and
one or more stop bits. In most applications the least significant data
bit (the one on the left in this diagram) is transmitted first, but
there are exceptions (such as the
The start bit signals the receiver that a new character is coming. The next five to nine bits, depending on the code set employed, represent the character. If a parity bit is used, it would be placed after all of the data bits. The next one or two bits are always in the MARK (logic high, i.e., '1') condition and called the stop bit(s). They signal the receiver that the character is completed. Since the start bit is logic low (0) and the stop bit is logic high (1) there are always at least two guaranteed signal changes between characters.
If the line is held in the logic low condition for longer than a character time, this is a break condition that can be detected by the UART.
All operations of the UART hardware are controlled by a clock signal which runs at a multiple of the data rate, typically 8 times the bit rate. The receiver tests the state of the incoming signal on each clock pulse, looking for the beginning of the start bit. If the apparent start bit lasts at least one-half of the bit time, it is valid and signals the start of a new character. If not, it is considered a spurious pulse and is ignored. After waiting a further bit time, the state of the line is again sampled and the resulting level clocked into a shift register. After the required number of bit periods for the character length (5 to 8 bits, typically) have elapsed, the contents of the shift register are made available (in parallel fashion) to the receiving system. The UART will set a flag indicating new data is available, and may also generate a processor interrupt to request that the host processor transfers the received data.
Communicating UARTs usually have no shared timing system apart from the communication signal. Typically, UARTs resynchronize their internal clocks on each change of the data line that is not considered a spurious pulse. Obtaining timing information in this manner, they reliably receive when the transmitter is sending at a slightly different speed than it should. Simplistic UARTs do not do this, instead they resynchronize on the falling edge of the start bit only, and then read the center of each expected data bit, and this system works if the broadcast data rate is accurate enough to allow the stop bits to be sampled reliably.
It is a standard feature for a UART to store the most recent character while receiving the next. This "double buffering" gives a receiving computer an entire character transmission time to fetch a received character. Many UARTs have a small first-in, first-out FIFO buffer memory between the receiver shift register and the host system interface. This allows the host processor even more time to handle an interrupt from the UART and prevents loss of received data at high rates.
Transmission operation is simpler as the timing does not have to be determined from the line state, nor is it bound to any fixed timing intervals. As soon as the sending system deposits a character in the shift register (after completion of the previous character), the UART generates a start bit, shifts the required number of data bits out to the line, generates and sends the parity bit (if used), and sends the stop bits. Since full-duplex operation requires characters to be sent and received at the same time, UARTs use two different shift registers for transmitted and received characters. High performance UARTs could contain a transmit FIFO (first in first out) buffer to allow a CPU or DMA controller to deposit multiple characters in a burst into the FIFO rather than have to deposit one character at a time into the FIFO. Since transmission of a single or multiple characters may take a long time relative to CPU speeds, a UART maintains a flag showing busy status so that the host system knows if there is at least one character in the transmit buffer or shift register; "ready for next character(s)" may also be signaled with an interrupt.
Transmitting and receiving UARTs must be set for the same bit speed, character length, parity, and stop bits for proper operation. The receiving UART may detect some mismatched settings and set a "framing error" flag bit for the host system; in exceptional cases the receiving UART will produce an erratic stream of mutilated characters and transfer them to the host system.
Typical serial ports used with personal computers connected to modems use eight data bits, no parity, and one stop bit; for this configuration the number of ASCII characters per second equals the bit rate divided by 10.
Some very low-cost home computers or embedded systems dispense with a UART and use the CPU to sample the state of an input port or directly manipulate an output port for data transmission. While very CPU-intensive (since the CPU timing is critical), the UART chip can thus be omitted, saving money and space. The technique is known as bit-banging .
Some early telegraph schemes used variable-length pulses (as in Morse code ) and rotating clockwork mechanisms to transmit alphabetic characters. The first serial communication devices (with fixed-length pulses) were rotating mechanical switches (commutators). Various character codes using 5, 6, 7, or 8 data bits became common in teleprinters and later as computer peripherals. The teletypewriter made an excellent general-purpose I/O device for a small computer.
DEC condensed the line unit design into an early single-chip UART for their own use. Western Digital developed this into the first widely available single-chip UART, the WD1402A, around 1971. This was an early example of a medium scale integrated circuit . Another popular chip was the SCN2651 from the Signetics 2650 family.
An example of an early 1980s UART was the
Depending on the manufacturer, different terms are used to identify
devices that perform the UART functions.
A UART usually contains the following components:
* a clock generator, usually a multiple of the bit rate to allow sampling in the middle of a bit period. * input and output shift registers * transmit/receive control * read/write control logic * transmit/receive buffers (optional) * system data bus buffer (optional) * First-in, first-out (FIFO ) buffer memory (optional) * Signals needed by a third party DMA controller (optional) * Integrated bus mastering DMA controller (optional)
SPECIAL TRANSCEIVER CONDITIONS
An "overrun error" occurs when the receiver cannot process the character that just came in before the next one arrives. Various devices have different amounts of buffer space to hold received characters. The CPU or DMA controller must service the UART in order to remove characters from the input buffer. If the CPU or DMA controller does not service the UART quickly enough and the buffer becomes full, an Overrun Error will occur, and incoming characters will be lost.
An "underrun error" occurs when the UART transmitter has completed sending a character and the transmit buffer is empty. In asynchronous modes this is treated as an indication that no data remains to be transmitted, rather than an error, since additional stop bits can be appended. This error indication is commonly found in USARTs, since an underrun is more serious in synchronous systems.
A "framing error" occurs when the designated "start" and "stop" bits are not found. As the "start" bit is used to identify the beginning of an incoming character, it acts as a reference for the remaining bits. If the data line is not in the expected state (hi/lo) when the "stop" bit is expected, a Framing Error will occur.
A Parity Error occurs when the parity of the number of 1 bits disagrees with that specified by the parity bit. Use of a parity bit is optional, so this error will only occur if parity-checking has been enabled.
A "break condition" occurs when the receiver input is at the "space" (logic low, i.e., '0') level for longer than some duration of time, typically, for more than a character time. This is not necessarily an error, but appears to the receiver as a character of all zero bits with a framing error. The term "break" derives from current loop signaling, which was the traditional signaling used for teletypewriters . The "spacing" condition of a current loop line is indicated by no current flowing, and a very long period of no current flowing is often caused by a break or other fault in the line.
Some equipment will deliberately transmit the "space" level for
longer than a character as an attention signal. When signaling rates
are mismatched, no meaningful characters can be sent, but a long
"break" signal can be a useful way to get the attention of a
mismatched receiver to do something (such as resetting itself).
A dual UART, or DUART, combines two UARTs into a single chip.
Similarly, a quadruple UART or QUART, combines four UARTs into one
package, such as the
WD1402A The first single-chip UART on general sale. Introduced about 1971. Compatible chips included the Fairchild TR1402A and the General Instruments AY-5-1013.
CDP 1854 (RCA, now Intersil)
2000 kbit/s. Universal Synchronous/Asynchronous
Receiver/Transmitter . Async, Bisync , SDLC , HDLC ,
Universal Synchronous/Asynchronous Receiver/Transmitter has a
3 byte receive buffer and a 1 byte transmit buffer. It has hardware to
accelerate the processing of HDLC and SDLC. The
8250 Obsolete with 1-byte buffers. These UARTs' maximum standard serial port speed is 9600 bits per second if the operating system has a 1 millisecond interrupt latency . 8250 UARTs were used in the IBM PC 5150 and IBM PC/XT, while the 16450 UART were used in IBM PC/AT -series computers.
This UART allows asynchronous operation up to 288 kbit/s, with two
independent four-byte FIFOs. It was produced by
16550 This UART's FIFO is broken, so it cannot safely run any faster than the 16450 UART. The 16550A and later versions fix this bug.
This UART has 16-byte FIFO buffers. Its receive interrupt trigger
levels can be set to 1, 4, 8, or 14 characters. Its maximum standard
serial port speed if the operating system has a 1 millisecond
interrupt latency is 115.2 kbit/s. Operating systems with lower
interrupt latencies could handle higher baud rates like 230.4 kbit/s
or 460.8 kbit/s. This chip can provide signals that are needed to
allow a third party DMA controller to perform DMA transfers to and
from the UART if the DMA mode this UART introduces is enabled. It was
introduced by National Semiconductor, which has been sold to Texas
16650 This UART was introduced by Startech Semiconductor which is now owned by Exar Corporation and is not related to Startech.com. Early versions have a broken FIFO buffer and therefore cannot safely run any faster than the 16450 UART. Versions of this UART that were not broken have 32-character FIFO buffers and could function at standard serial port speeds up to 230.4 kbit/s if the operating system has a 1 millisecond interrupt latency. Current versions of this UART by Exar claim to be able to handle up to 1.5 Mbit/s. This UART introduces the Auto-RTS and Auto-CTS features in which the RTS# signal is controlled by the UART to signal the external device to stop transmitting when the UART's buffer is full to or beyond a user-set trigger point and to stop transmitting to the device when the device drives the CTS# signal high (logic 0).
16750 64-byte buffers. This UART can handle a maximum standard serial port speed of 460.8 kbit/s if the maximum interrupt latency is 1 millisecond. This UART was introduced by Texas Instruments. TI claims that early models can run up to 1 Mbit/s, and later models can run up to 5 Mbit/s.
16850 128-byte buffers. This UART can handle a maximum standard serial port speed of 921.6 kbit/s if the maximum interrupt latency is 1 millisecond. This UART was introduced by Exar Corporation. Exar claims that early models can run up to 1.5 Mbit/s, and later models can run up to 6.25 Mbit/s.
16950 128-byte buffers. This UART can handle a maximum standard serial port speed of 921.6 kbit/s if the maximum interrupt latency is 1 millisecond. This UART supports 9-bit characters in addition to the 5-8 bit characters that other UARTs support. This was introduced by Oxford Semiconductor, which is now owned by PLX Technology. Oxford/PLX claims that this UART can run up to 15 Mbit/s. PCI Express variants by Oxford/PLX are integrated with a first party bus mastering PCIe DMA controller. This DMA controller is controlled by the UART's DMA mode signals that were defined for the 16550. The DMA controller requires the CPU to set up each transaction and poll a status register after the transaction is started to determine if the transaction is done. Each DMA transaction can transfer between 1 and 128 bytes between a memory buffer and the UART. PCI Express variants can also allow the CPU to transfer data between itself and the UART with 8, 16, or 32 bit transfers when using programmed I/O.
16954 Quad port version of the 16950/16C950. 128-byte buffers. This UART can handle a maximum standard serial port speed of 921.6 kbit/s if the maximum interrupt latency is 1 millisecond. This UART supports 9-bit characters in addition to the 5-8 bit characters that other UARTs support. This was introduced by Oxford Semiconductor, which is now owned by PLX Technology. Oxford/PLX claims that this UART can run up to 15 Mbit/s. PCI Express variants by Oxford/PLX are integrated with a first party bus mastering PCIe DMA controller. This DMA controller is controlled by the UART's DMA mode signals that were defined for the 16550. The DMA controller requires the CPU to set up each transaction and poll a status register after the transaction is started to determine if the transaction is done. Each DMA transaction can transfer between 1 and 128 bytes between a memory buffer and the UART. PCI Express variants can also allow the CPU to transfer data between itself and the UART with 8, 16, or 32 bit transfers when using programmed I/O.
16C1550/16C1551 UART with 16-byte FIFO buffers. Up to 1.5 Mbit/s. The ST16C155X is not compatible with the industry standard 16550 and will not work with the standard serial port driver in Microsoft Windows.
16C2450 Dual UART with 1-byte FIFO buffers.
16C2550 Dual UART with 16-byte FIFO buffers. Pin-to-pin and functional compatible to 16C2450. Software compatible with INS8250 and NS16C550.
Currently produced by
The 28L91 is an upwardly compatible version of the 2691, featuring selectable 8- or 16-byte transmitter and receiver FIFOs, improved support for extended data rates, and faster bus timing characteristics, making the device more suitable for use with high performance microprocessors.
Both the 2691 and 28L91 may also be operated in TIA-422 and TIA-485
modes, and may also be programmed to support non-standard data rates.
The devices are produced in PDIP-40, PLCC-44 and 44 pin QFP packages,
and are readily adaptable to both
SCC2692 Currently produced by NXP, these devices are dual UARTs (DUART), consisting of two communications channels, associated control registers and one counter/timer. Each communication channel is independently programmable and supports independent transmit and receive data rates.
The 2692 has a single byte transmitter holding register and a 4-byte receiver FIFO for each channel. Maximum standard speed of both of the 2692's channels is 115.2 kbit/s.
The 26C92 is an upwardly compatible version of the 2692, with 8-byte
transmitter and receiver FIFOs for improved performance during
continuous bi-directional asynchronous transmission (CBAT) on both
channels at the maximum standard speed of 230.4 kbit/s. The letter C
in the 26C92 part number has nothing to do with the fabrication
The 28L92 is an upwardly compatible version of the 26C92, featuring selectable 8- or 16-byte transmitter and receiver FIFOs, improved support for extended data rates, and faster bus timing characteristics, making the device more suitable for use with high performance microprocessors.
The 2692, 26C92 and 28L92 may be operated in TIA-422 and TIA-485
modes, and may also be programmed to support non-standard data rates.
The devices are produced in PDIP-40, PLCC-44 and 44 pin QFP packages,
and are readily adaptable to both
Currently produced by NXP, the 28C94 quadruple UART (QUART) is
functionally similar to a pair of SCC26C92 DUARTs mounted in a common
package, with the addition of an arbitrated interrupt system for
efficient processing during periods of intense channel activity. Some
additional signals are present to support the interrupt management
features and the auxiliary input/output pins are arranged differently
than those of the 26C92. Otherwise, the programming model for the
28C94 is similar to that of the 26C92, requiring only minor code
changes to fully utilize all features. The 28C94 supports a maximum
standard speed of 230.4 kbit/s, is available in a PLCC-52 package, and
is readily adaptable to both
Currently produced by NXP, the 2698 octal UART (OCTART) is
essentially four SCC2692 DUARTs in a single package. Specifications
are the same as the SCC2692 (not the SCC26C92). Due to the lack of
transmitter FIFOs and the small size of the receiver FIFOs, the 2698
can cause an interrupt "storm" if all channels are simultaneously
engaged in continuous bi-directional communication. The device is
produced in PDIP-64 and PLCC-84 packages, and is readily adaptable to
Currently produced by NXP, the 28L198 OCTART is essentially an
upscaled enhancement of the SCC28C94 QUART described above, with eight
independent communications channels, as well as an arbitrated
interrupt system for efficient processing during periods of intense
channel activity. The 28L198 supports a maximum standard speed of
460.8 kbit/s, is available in PLCC-84 and LQFP-100 packages, and is
readily adaptable to both
Z85230 Synchronous/Asynchronous modes, 2 ports. Provides signals needed by a third party DMA controller needed to perform DMA transfers. 4-byte buffer to send, 8-byte buffer to receive per channel. SDLC/HDLC modes. 5 Mbit/s in synchronous mode.
Hayes ESP 1 kB buffers, 921.6 kbit/s, 8-ports.
Exar XR17V352, XR17V354 and XR17V358 Dual, Quad and Octal PCI Express UARTs with 16550 compatible register Set, 256-byte TX and RX FIFOs, Programmable TX and RX Trigger Levels, TX/RX FIFO Level Counters, Fractional baud rate generator, Automatic RTS/CTS or DTR/DSR hardware flow control with programmable hysteresis, Automatic Xon/Xoff software flow control, RS-485 half duplex direction control output with programmable turn-around delay, Multi-drop with Auto Address Detection, Infrared (IrDA 1.1) data encoder/decoder. They are specified up to 25 Mbit/s. DataSheets are dated from 2012.
Exar XR17D152, XR17D154 and XR17D158 Dual, Quad and Octal PCI bus UARTs with 16C550 Compatible 5G Register Set, 64-byte Transmit and Receive FIFOs, Transmit and Receive FIFO Level Counters, Programmable TX and RX FIFO Trigger Level, Automatic RTS/CTS or DTR/DSR Flow Control, Automatic Xon/Xoff Software Flow Control, RS485 HDX Control Output with Selectable Turn-around Delay, Infrared (IrDA 1.0) Data Encoder/Decoder, Programmable Data Rate with Prescaler, Up to 6.25 Mbit/s Serial Data Rate. DataSheets are dated from 2004 and 2005.
Exar XR17C152, XR17C154 and XR17C158 Dual, Quad and Octal 5V PCI bus UARTs with 16C550 Compatible Registers, 64-byte Transmit and Receive FIFOs, Transmit and Receive FIFO Level Counters, Automatic RTS/CTS or DTR/DSR Flow Control, Automatic Xon/Xoff Software Flow Control, RS485 Half-duplex Control with Selectable Delay, Infrared (IrDA 1.0) Data Encoder/Decoder, Programmable Data Rate with Prescaler, Up to 6.25 Mbit/s Serial Data Rate. DataSheets are dated from 2004 and 2005.
Exar XR17V252, XR17V254 and XR17V258 Dual, Quad and Octal 66 MHz PCI bus UARTs with Power Management Support, 16C550 compatible register set, 64-byte TX and RX FIFOs with level counters and programmable trigger levels, Fractional baud rate generator, Automatic RTS/CTS or DTR/DS