|
Functional Verification
In electronic design automation, functional verification is the task of verifying that the logic design conforms to specification. Functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, and takes the majority of time and effort in most large electronic system design projects. Functional verification is a part of more encompassing ''design verification'', which, besides functional verification, considers non-functional aspects like timing, layout and power. Functional verification is very difficult because of the sheer volume of possible test-cases that exist in even a simple design. Frequently there are more than 10^80 possible tests to comprehensively verify a design – a number that is impossible to achieve in a lifetime. This effort is equivalent to program verification, and is NP-hard or even worse – and no solution has been found that works well in all cases. However, it can be attacked by many m ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Electronic Design Automation
Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD), is a category of software tools for designing electronic systems such as integrated circuits and printed circuit boards. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. Since a modern semiconductor chip can have billions of components, EDA tools are essential for their design; this article in particular describes EDA specifically with respect to integrated circuits (ICs). History Early days Prior to the development of EDA, integrated circuits were designed by hand and manually laid out. Some advanced shops used geometric software to generate tapes for a Gerber photoplotter, responsible for generating a monochromatic exposure image, but even those copied digital recordings of mechanically drawn components. The process was fundamentally graphic, with the translation from electronics to graphics done manu ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Code Coverage
In computer science, test coverage is a percentage measure of the degree to which the source code of a program is executed when a particular test suite is run. A program with high test coverage has more of its source code executed during testing, which suggests it has a lower chance of containing undetected software bugs compared to a program with low test coverage. Many different metrics can be used to calculate test coverage. Some of the most basic are the percentage of program subroutines and the percentage of program statements called during execution of the test suite. Test coverage was among the first methods invented for systematic software testing. The first published reference was by Miller and Maloney in ''Communications of the ACM'', in 1963. Coverage criteria To measure what percentage of code has been executed by a test suite, one or more ''coverage criteria'' are used. These are usually defined as rules or requirements, which a test suite must satisfy. Basic c ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
High-level Verification
High-level verification (HLV), or electronic system-level (ESL) verification, is the task to verify ESL designs at high abstraction level, i.e., it is the task to verify a model that represents hardware above register-transfer level (RTL) abstract level. For high-level synthesis (HLS or C synthesis), HLV is to HLS as functional verification is to logic synthesis. Electronic digital hardware design has evolved from low level abstraction at gate level to register transfer level (RTL), the abstraction level above RTL is commonly called high-level, ESL, or behavioral/algorithmic level. In high-level synthesis, behavioral/algorithmic designs in ANSI C/C++/SystemC code is synthesized to RTL, which is then synthesized into gate level through logic synthesis. Functional verification is the task to make sure a design at RTL or gate level conforms to a specification. As logic synthesis matures, most functional verification is done at the higher abstraction, i.e. at RTL level, the correctnes ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Cleanroom Software Engineering
The cleanroom software engineering process is a software development process intended to produce software with a certifiable level of reliability. The cleanroom process was originally developed by Harlan Mills and several of his colleagues including Alan Hevner at IBM. The focus of the cleanroom process is on defect prevention, rather than defect removal. The name "cleanroom" was chosen to evoke the cleanrooms used in the electronics industry to prevent the introduction of defects during the fabrication of semiconductors. The cleanroom process first saw use in the mid to late 1980s. Demonstration projects within the military began in the early 1990s. Recent work on the cleanroom process has examined fusing cleanroom with the automated verification capabilities provided by specifications expressed in CSP. Central principles The basic principles of the cleanroom process are ;Software development based on formal methods: Software tool support based on some mathematical form ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Analog Verification
Analog verification is a methodology for performing functional verification on analog, mixed-signal and RF integrated circuits and systems on chip.Henry Chang and Ken KundertVerification of Complex Analog and RF IC Designs ''Proceedings of the IEEE'', February 2007. Discussion of analog verification began in 2005 when it started to become recognized that the analog portion of large mixed-signal chips had become so complex that a significant and ever increasing number of these chips were being designed with functional errors in the analog portion that prevented them from operating correctly. Technical details Analog verification is built on the idea that transistor level simulation will always be too slow to provide adequate functional verification. Instead, it is necessary to build simple and efficient models of the blocks that make up the analog portion of the design and use those to verify the design. Those models are typically written in Verilog or Verilog-AMS, but could ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Synopsys
Synopsys is an American electronic design automation (EDA) company that focuses on silicon design and verification, silicon intellectual property and software security and quality. Products include tools for logic synthesis and physical design of integrated circuits, simulators for development and debugging environments that assist in the design of the logic for chips and computer systems. In recent years, Synopsys has expanded its products and services to include application security testing. Synopsys has gained attention due to its relationship with various Chinese state entities. In 2018, Synopsys formed a partnership with the People's Liberation Army National Defence University and, in 2022, the company came under investigation by the United States Department of Justice for technology transfers to sanctioned entities in China. History Synopsys was founded by Aart J de Geus and David Gregory in 1986 in Research Triangle Park, North Carolina. The company was initi ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Nusym Technology
Nusym Technology, Inc. was a company that produced intelligent verification software products, also known as ''intelligent testbench'' products, which are a form of functional verification that targets and maximizes test coverage of a logic design by automatically adapting the verification testbenches to changes in register transfer level In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those ... code. History The company was founded in 2004 by Chris Wilson, {{Webarchive, url=https://web.archive.org/web/20111003070427/http://www.scdsource.com/article.php?id=197 , date=2011-10-03 Ken Imboden and Dave Gold. The company had offices in California and Bangalore. It was acquir ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Mentor Graphics
Siemens EDA is a US-based electronic design automation (EDA) multinational corporation for electrical engineering and electronics, headquartered in Wilsonville, Oregon. Founded in 1981 as Mentor Graphics, the company was acquired by Siemens in 2017. The company distributes products that assist in electronic design automation, simulation tools for analog mixed-signal design, VPN solutions, and fluid dynamics and heat transfer tools. The company leveraged Apollo Computer workstations to differentiate itself within the computer-aided engineering (CAE) market with its software and hardware. History Siemens EDA was founded as Mentor Graphics in 1981 by Tom Bruggere, Gerry Langeler, and Dave Moffenbeier, all formerly of Tektronix. The company raised $55 million in funding through an initial public offering in 1984. Mentor initially wrote software that ran only in Apollo workstations. When Mentor entered the CAE market the company had two technical differentiators: the fi ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
EVE/ZeBu
EVE/ZeBu is a provider of hardware-assisted verification tools for functional verification of Application-specific integrated circuits (ASICs) and system on chip (SOC) designs and for validation of embedded software (software driver, Operating System and Application software) ahead of implementation in silicon. EVE's hardware acceleration and hardware emulation products work in conjunction with Verilog, SystemVerilog, and VHDL-based simulators from Synopsys, Cadence Design Systems and Mentor Graphics. EVE's flagship product is ZeBu. History In 2000, EVE was founded in France. In 2002, EVE launched its flagship ZeBu's first emulation product and SystemC support. In May 2006, EVE introduced a communication link to SystemVerilog simulation, SystemVerilog assertion support, and a register transfer level compiler for mapping an ASIC or System-on-a-chip (SOC) design into ZeBu's arrays of FPGAs. In January 2007, EVE acquired Tharas, a microprocessor-based hardware acceleratio ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Cadence Design Systems
Cadence Design Systems, Inc. (stylized as cādence), headquartered in San Jose, California, is an American multinational computational software company, founded in 1988 by the merger of SDA Systems and ECAD, Inc. The company produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards. History Origins Cadence Design Systems began as an electronic design automation (EDA) company, formed by the 1988 merger of Solomon Design Automation (SDA), co-founded in 1983 by Richard Newton, Alberto Sangiovanni-Vincentelli and James Solomon, and ECAD, a public company co-founded by Ping Chao, Glen Antle and Paul Huang in 1982. SDA's CEO Joseph Costello was appointed as CEO of the newly combined company. Executive leadership Following the resignation of Cadence's original CEO Joe Costello in 1997, Jack Harding was appointed CEO. Ray Bingham was named CEO in 1999. In 2004, Mike Fister became Cadence's new CEO. ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
