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ESi-RISC
eSi-RISC is a configurable CPU architecture. It is available in five implementations: the eSi-1600, eSi-1650, eSi-3200, eSi-3250 and eSi-3264. The eSi-1600 and eSi-1650 feature a 16-bit data-path, while the eSi-32x0s feature 32-bit data-paths, and the eSi-3264 features a mixed 32/64-bit datapath. Each of these processors is licensed as soft IP cores, suitable for integrating into both ASICs and FPGAs. Architecture The main features of the eSi-RISC architecture are: * RISC-like load/store architecture. * Configurable 16-bit, 32-bit or 32/64-bit data-path. * Instructions are encoded in either 16 or 32-bits. * 8, 16 or 32 general purpose registers, that are either 16 or 32-bits wide. * 0, 8, 16 or 32 vector registers, that are either 32 or 64-bits wide. * Up to 32 external, vectored, nested and prioritizable interrupts. * Configurable instruction set including support for integer, floating-point and fixed-point arithmetic. * SIMD operations. * Optional support for user-defined ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Phoenix-RTOS
Phoenix-RTOS is a real-time operating system designed for Internet of Things appliances. The main goal of the system is to facilitate the creation of "Software Defined Solutions". History Phoenix-RTOS is the successor to the Phoenix operating system, developed from 1999 to 2001 by Pawel Pisarczyk at the Department of Electronics and Information Technology at Warsaw University of Technology. Phoenix was originally implemented for IA-32 microprocessors and was adapted to the ARM7TDMI processor in 2003, and the PowerPC in 2004. The system is available under the GPL license. Phoenix-RTOS 2.0 The decision to abandon the development of Phoenix and write the Phoenix-RTOS from scratch was taken by its creator in 2004. In 2010, the Phoenix Systems company was established, aiming to commercialize the system. Phoenix-RTOS 2.0 is based on a monolithic kernel. Initially versions for the IA-32 processor and configurable eSi-RISC were developed. In cooperation with NXP Semiconductor ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
GNU Compiler Collection
The GNU Compiler Collection (GCC) is an optimizing compiler produced by the GNU Project supporting various programming languages, hardware architectures and operating systems. The Free Software Foundation (FSF) distributes GCC as free software under the GNU General Public License (GNU GPL). GCC is a key component of the GNU toolchain and the standard compiler for most projects related to GNU and the Linux kernel. With roughly 15 million lines of code in 2019, GCC is one of the biggest free programs in existence. It has played an important role in the growth of free software, as both a tool and an example. When it was first released in 1987 by Richard Stallman, GCC 1.0 was named the GNU C Compiler since it only handled the C programming language. It was extended to compile C++ in December of that year. Front ends were later developed for Objective-C, Objective-C++, Fortran, Ada, D and Go, among others. The OpenMP and OpenACC specifications are also supported in the C ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ERIKA Enterprise
ERIKA Enterprise is a real-time operating system (RTOS) kernel for embedded systems, which is OSEK/VDX certified. It is free and open source software released under a GNU General Public License (GPL). The RTOS also includes RT-Druid, an integrated development environment (IDE) based on Eclipse. ERIKA Enterprise implements various conformance classes, including the standard OSEK/VDX conformance classes BCC1, BCC2, ECC1, ECC2, CCCA, and CCCB. Also, ERIKA provides other custom conformance classes named FP (fixed priority), EDF (''earliest deadline first'' scheduling), and FRSH (an implementation of resource reservation protocols). Due to the collaboration with the Tool & Methodologies team of Magneti Marelli Powertrain & Electronics, the automotive kernel (BCC1, BCC2, ECC1, ECC2, multicore, memory protection, and kernel fixed priority with Diab 5.5.1 compiler) is MISRA C 2004 compliant using FlexeLint 9.00h under the configuration suggested by Magneti Marelli. In August 2012 ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
FreeRTOS
FreeRTOS is a real-time operating system kernel for embedded devices that has been ported to 35 microcontroller platforms. It is distributed under the MIT License. History The FreeRTOS kernel was originally developed by Richard Barry around 2003, and was later developed and maintained by Barry's company, Real Time Engineers Ltd. In 2017, the firm passed stewardship of the FreeRTOS project to Amazon Web Services (AWS). Barry continues to work on FreeRTOS as part of an AWS team. Implementation FreeRTOS is designed to be small and simple. It is mostly written in the C programming language to make it easy to port and maintain. It also comprises a few assembly language functions where needed, mostly in architecture-specific scheduler routines. Process management FreeRTOS provides methods for multiple threads or tasks, mutexes, semaphores and software timers. A tickless mode is provided for low power applications. Thread priorities are supported. FreeRTOS applications can ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
MicroC/OS-II
Micro-Controller Operating Systems (MicroC/OS, stylized as μC/OS) is a real-time operating system (RTOS) designed by Jean J. Labrosse in 1991. It is a priority-based preemptive real-time kernel for microprocessors, written mostly in the programming language C. It is intended for use in embedded systems. MicroC/OS allows defining several functions in C, each of which can execute as an independent thread or task. Each task runs at a different priority, and runs as if it owns the central processing unit (CPU). Lower priority tasks can be preempted by higher priority tasks at any time. Higher priority tasks use operating system (OS) services (such as a delay or event) to allow lower priority tasks to execute. OS services are provided for managing tasks and memory, communicating between tasks, and timing. History The MicroC/OS kernel was published originally in a three-part article in Embedded Systems Programming magazine and the book ''μC/OS The Real-Time Kernel'' by Labrosse. He ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
16-bit
16-bit microcomputers are microcomputers that use 16-bit microprocessors. A 16-bit register can store 216 different values. The range of integer values that can be stored in 16 bits depends on the integer representation used. With the two most common representations, the range is 0 through 65,535 (216 − 1) for representation as an ( unsigned) binary number, and −32,768 (−1 × 215) through 32,767 (215 − 1) for representation as two's complement. Since 216 is 65,536, a processor with 16-bit memory addresses can directly access 64 KB (65,536 bytes) of byte-addressable memory. If a system uses segmentation with 16-bit segment offsets, more can be accessed. 16-bit architecture The MIT Whirlwind ( 1951) was quite possibly the first-ever 16-bit computer. It was an unusual word size for the era; most systems used six-bit character code and used a word length of some multiple of 6-bits. This changed with the effort to introduce ASCII, which used a 7-bit code and naturally ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
RISC
In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set computer (CISC), a RISC computer might require more instructions (more code) in order to accomplish a task because the individual instructions are written in simpler code. The goal is to offset the need to process more instructions by increasing the speed of each instruction, in particular by implementing an instruction pipeline, which may be simpler given simpler instructions. The key operational concept of the RISC computer is that each instruction performs only one function (e.g. copy a value from memory to a register). The RISC computer usually has many (16 or 32) high-speed, general-purpose registers with a load/store architecture in which the code for the register-register instructions (for performing arithmetic and tests) are separate ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
IP Core
In electronic design, a semiconductor intellectual property core (SIP core), IP core, or IP block is a reusable unit of logic, cell, or integrated circuit layout design that is the intellectual property of one party. IP cores can be licensed to another party or owned and used by a single party. The term comes from the licensing of the patent or source code copyright that exists in the design. Designers of application-specific integrated circuits (ASIC) and systems of field-programmable gate array (FPGA) logic can use IP cores as building blocks. History The licensing and use of IP cores in chip design came into common practice in the 1990s. There were many licensors and also many foundries competing on the market. In 2013, the most widely licensed IP cores are from Arm Holdings (43.2% market share), Synopsys Inc. (13.9% market share), Imagination Technologies (9% market share) and Cadence Design Systems (5.1% market share). Types of IP cores The use of an IP core in chip desi ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Application-specific Integrated Circuit
An application-specific integrated circuit (ASIC ) is an integrated circuit (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a digital voice recorder or a high-efficiency video codec. Application-specific standard product (ASSP) chips are intermediate between ASICs and industry standard integrated circuits like the 7400 series or the 4000 series. ASIC chips are typically fabricated using metal-oxide-semiconductor (MOS) technology, as MOS integrated circuit chips. As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 logic gates to over 100 million. Modern ASICs often include entire microprocessors, memory blocks including ROM, RAM, EEPROM, flash memory and other large building blocks. Such an ASIC is often termed a SoC (system-on-chip). Designers of digital ASICs often use a hardware descr ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
FPGA
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturinghence the term '' field-programmable''. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). Circuit diagrams were previously used to specify the configuration, but this is increasingly rare due to the advent of electronic design automation tools. FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable interconnects allowing blocks to be wired together. Logic blocks can be configured to perform complex combinational functions, or act as simple logic gates like AND and XOR. In most FPGAs, logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. Many FPGAs can be reprogrammed to implement different logic functions, allowing flexible reconfigu ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
RTOS
A real-time operating system (RTOS) is an operating system (OS) for real-time applications that processes data and events that have critically defined time constraints. An RTOS is distinct from a time-sharing operating system, such as Unix, which manages the sharing of system resources with a scheduler, data buffers, or fixed task prioritization in a multitasking or multiprogramming environment. Processing time requirements need to be fully understood and bound rather than just kept as a minimum. All processing must occur within the defined constraints. Real-time operating systems are event-driven and preemptive, meaning the OS is capable of monitoring the relevant priority of competing tasks, and make changes to the task priority. Event-driven systems switch between tasks based on their priorities, while time-sharing systems switch the task based on clock interrupts. Characteristics A key characteristic of an RTOS is the level of its consistency concerning the amount of time i ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
