eSi-RISC is a configurable CPU architecture. It is available in five implementations: the eSi-1600, eSi-1650, eSi-3200, eSi-3250 and eSi-3264. The eSi-1600 and eSi-1650 feature a

16-bit 16-bit microcomputers are microcomputers that use 16-bit microprocessors. A 16-bit register can store 216 different values. The range of integer values that can be stored in 16 bits depends on the integer representation used. With the two mos ...

data-path, while the eSi-32x0s feature

32-bit In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in 32-bit units. Compared to smaller bit widths, 32-bit computers can perform large calculation ...

data-paths, and the eSi-3264 features a mixed 32/64-bit datapath. Each of these processors is licensed as soft

IP core In electronic design, a semiconductor intellectual property core (SIP core), IP core, or IP block is a reusable unit of logic, cell, or integrated circuit layout design that is the intellectual property of one party. IP cores can be licensed to ...

s, suitable for integrating into both

ASIC An application-specific integrated circuit (ASIC ) is an integrated circuit (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a digital voice recorder or a high-efficien ...

s and

FPGA A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturinghence the term '' field-programmable''. The FPGA configuration is generally specified using a hardware de ...

Architecture

The main features of the eSi-RISC architecture are: *

RISC In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set comput ...

-like load/store architecture. * Configurable 16-bit, 32-bit or 32/64-bit data-path. * Instructions are encoded in either 16 or 32-bits. * 8, 16 or 32 general purpose registers, that are either 16 or 32-bits wide. * 0, 8, 16 or 32 vector registers, that are either 32 or 64-bits wide. * Up to 32 external, vectored, nested and prioritizable interrupts. * Configurable instruction set including support for integer, floating-point and fixed-point arithmetic. *

SIMD Single instruction, multiple data (SIMD) is a type of parallel processing in Flynn's taxonomy. SIMD can be internal (part of the hardware design) and it can be directly accessible through an instruction set architecture (ISA), but it should ...

operations. * Optional support for user-defined instructions, such as cryptographic acceleration . * Optional caches (Configurable size and associativity). * Optional MMU supporting both memory protection and dynamic address translation. *

AMBA Amba or AMBA may refer to: Title * Amba Hor, alternative name for Abhor and Mehraela, Christian martyrs * Amba Sada, also known as Psote, Christian bishop and martyr in Upper Egypt Given name * Amba, the traditional first name given to the first ...

AXI, AHB and APB bus interfaces. * Memory mapped I/O. * 5-stage pipeline. * Hardware

JTAG JTAG (named after the Joint Test Action Group which codified it) is an Technical standard, industry standard for verifying designs and testing printed circuit boards after manufacture. JTAG implements standards for on-chip instrumentation in ele ...

debug. While there are many different 16 or 32-bit

Soft microprocessor A soft microprocessor (also called softcore microprocessor or a soft processor) is a microprocessor core that can be wholly implemented using logic synthesis. It can be implemented via different semiconductor devices containing programmable logic ...

IP cores available, eSi-RISC is the only architecture licensed as an IP core that has both 16 and 32-bit implementations. Unlike in other RISC architectures supporting both 16 and 32-bit instructions, such as ARM/Thumb or MIPS/MIPS-16, 16 and 32-bit instructions in the eSi-RISC architecture can be freely intermixed, rather than having different modes where either all 16-bit instructions or all 32-bit instructions are executed. This improves code density without compromising performance. The 16-bit instructions support two register operands in the lower 16 registers, whereas the 32-bit instructions support three register operands and access to all 32 registers. eSi-RISC includes support for

Multiprocessing Multiprocessing is the use of two or more central processing units (CPUs) within a single computer system. The term also refers to the ability of a system to support more than one processor or the ability to allocate tasks between them. There ar ...

. Implementations have included up to seven eSi-3250's on a single chip.

Toolchain

The eSi-RISC toolchain is based on combination of a port of the

GNU toolchain The GNU toolchain is a broad collection of programming tools produced by the GNU Project. These tools form a toolchain (a suite of tools used in a serial manner) used for developing software applications and operating systems. The GNU toolchain pl ...

and the

Eclipse An eclipse is an astronomical event that occurs when an astronomical object or spacecraft is temporarily obscured, by passing into the shadow of another body or by having another body pass between it and the viewer. This alignment of three ce ...

IDE. This includes: * GCC – C/C++ compiler. *

Binutils The GNU Binary Utilities, or , are a set of programming tools for creating and managing binary programs, object files, libraries, profile data, and assembly source code. Tools They were originally written by programmers at Cygnus Solutions. ...

– Assembler, linker and binary utilities. *

GDB The GNU Debugger (GDB) is a Software portability, portable debugger that runs on many Unix-like systems and works for many programming languages, including Ada (programming language), Ada, C (programming language), C, C++, Objective-C, Free Pasc ...

– Debugger. *

– Integrated Development Environment. The C library is

Newlib Newlib is a C standard library implementation intended for use on embedded systems. It is a conglomeration of several library parts, all under free software licenses that make them easily usable on embedded products. It was created by Cygnus S ...

and the C++ library is

Libstdc++ #REDIRECT C++ Standard Library The C standard library or libc is the standard library for the C programming language, as specified in the ISO C standard.ISO/IEC (2018). '' ISO/IEC 9899:2018(E): Programming Languages - C §7'' Starting from the ...

. Ported

RTOS A real-time operating system (RTOS) is an operating system (OS) for real-time applications that processes data and events that have critically defined time constraints. An RTOS is distinct from a time-sharing operating system, such as Unix, which ...

es include

MicroC/OS-II Micro-Controller Operating Systems (MicroC/OS, stylized as μC/OS) is a real-time operating system (RTOS) designed by Jean J. Labrosse in 1991. It is a priority-based preemptive real-time kernel for microprocessors, written mostly in the programm ...

FreeRTOS FreeRTOS is a real-time operating system kernel for embedded devices that has been ported to 35 microcontroller platforms. It is distributed under the MIT License. History The FreeRTOS kernel was originally developed by Richard Barry around ...

ERIKA Enterprise ERIKA Enterprise is a real-time operating system (RTOS) kernel for embedded systems, which is OSEK/VDX certified. It is free and open source software released under a GNU General Public License (GPL). The RTOS also includes RT-Druid, an integrat ...

and

Phoenix-RTOS Phoenix-RTOS is a real-time operating system designed for Internet of Things appliances. The main goal of the system is to facilitate the creation of "Software Defined Solutions". History Phoenix-RTOS is the successor to the Phoenix operatin ...

Cambridge Network 2013

References

External links

eSi-RISC homepage
{{DEFAULTSORT:Esi-Risc Soft microprocessors