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Xtensa
Tensilica was a company based in Silicon Valley in the semiconductor intellectual property core business. It is now a part of Cadence Design Systems. Tensilica is known for its customizable Xtensa microprocessor core. Other products include: HiFi audio/voice DSPs (digital signal processors) with a software library of over 225 codecs from Cadence and over 100 software partners; Vision DSPs that handle complex algorithms in imaging, video, computer vision, and neural networks; and the ConnX family of baseband DSPs ranging from the dual- MAC ConnX D2 to the 64-MAC ConnX BBE64EP. Tensilica was founded in 1997 by Chris Rowen (one of the founders of MIPS Technologies). It employed Earl Killian, who contributed to the MIPS architecture, as director of architecture. On March 11, 2013, Cadence Design Systems announced its intent to buy Tensilica for approximately $380 million in cash. Cadence completed the acquisition in April 2013, with a cash outlay at closing of approximately $326 mill ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Tensilica Instruction Extension
Tensilica Instruction Extension refers to the proprietary language that is used to customize Tensilica's Xtensa processor core architecture. By using TIE, the user can customize the Xtensa architecture by adding custom instructions and register files, instantiating TIE Ports and Queues for multiprocessor communication, and adding pre-configured extensions (such as Tensilica's DSP). Software applications can greatly benefit from properly targeted user-defined instructions, while TIE ports and TIE queues facilitate multiprocessor communication by adding separate input and output interfaces to the processor core. Using the TIE language and Xtensa Xplorer toolkit, the generation and verification of the instructions used to extend the processor ISA are automated. Such automation helps to reduce the hardware verification time that typically consumes a large percentage of the project duration of a typical hardware developed for the same functionality. History TIE was added by Tensilic ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Very Long Instruction Word
Very long instruction word (VLIW) refers to instruction set architectures designed to exploit instruction level parallelism (ILP). Whereas conventional central processing units (CPU, processor) mostly allow programs to specify instructions to execute in sequence only, a VLIW processor allows programs to explicitly specify instructions to execute in parallel. This design is intended to allow higher performance without the complexity inherent in some other designs. Overview The traditional means to improve performance in processors include dividing instructions into substeps so the instructions can be executed partly at the same time (termed ''pipelining''), dispatching individual instructions to be executed independently, in different parts of the processor (''superscalar architectures''), and even executing instructions in an order different from the program (''out-of-order execution''). These methods all complicate hardware (larger circuits, higher cost and energy use) because ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
